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Error When Running AMS Simulations with Both VHDL and Verilog in Digital Heirarchy

amrao

Hello,

I am attempting to run an AMS simulation including a digital block consisting of both VHDL and Verilog in the digital heriarchy.

The question is in two parts. The first part relates to how I'm setting up the simulation as maybe that's where I'm going

wrong. The second part is the error I'm getting during compilation.

First Part: I have a digital behavioral block with multiple levels of hierarchy. I read in the top level block using Verilog-In to

create a symbol view. I then instantiate this block in a test bench schematic and use the Hierarchy Editor to point to the 

symbol view. In the Simulator->AMS Options form I include all the Verilog files and VHDL files in the Netlister tab for the whole

digital hierarchy including the top level. Is this a valid way of running AMS using a digital block with hierarchy or is there 

something fundamentally wrong with this approach?

Second Part: I set the simulator to 'ams' and the 'Netlist and Run Options' to use the OSS-based netlister with irun' The design

netlists with no problems but the compiler fails when it tries to compile the VHDL blocks with 'expecting the keywork 'module' and

numerous errors of 'illegal base specification'. My understanding is that irun should be able to run with both VHDL and Verilog at the

same time but it seems there is a problem with the VHDL blocks.

Thank you for any help,

Anand

Parents

  • Anand,

    This seems a reasonable approach, although my guess is that you're using an old version (the OSS-based netlister is obsolete and isn't even there in current versions of the tool). You should be using the Unified Netlister, and you should be using XCELIUM rather than INCISIVE. I don't think that's necessarily the reason for your problem because what you're doing ought to be possible in general.

    So, please provide:

    1. Which IC subversion you're using (Help->About will tell you this - please list the complete version)
    2. Which INCISIVE (or ideally XCELIUM) sub-version are you using? The simulator log file will tell you this
    3. Please show a screenshot of how you've included the files

    Regards,

    Andrew

  • in reply to Andrew Beckett

    Hi Andrew,

    Thank you very much for the quick reply.

    1. IC6.1.6-64b.500.8

    2. irun(64) 15.20-s072 (Is this Incisive?)

    3. Below I've included all the verilog and vhdl files in the 'Include Files' in the 'Netlister' tab.

    -Anand

  • in reply to amrao

    Hello,

    I have an update on this issue. Our digital designer was able to convert the VHDL block to a Verilog block. I now

    take a different approach where I import all the blocks to create Functional views and then point the top level digital

    block to use the functional view instead of including all the files as before. This brings the entire digital hierarchy into

    the Config view.

    Now the AMS simulation runs with all Verilog blocks but still fails when I try to use the VHDL view which is imported as an 'rtl'

    view. The error in the simulation log file is just 'failed to compile module' for the VHDL block. A screen capture of the logfile

    utility is attached below. 

    Logfile Utility

    We would still like to be able to use both Verilog and VHDL views since there is a mix allowed for the project.

    Best Regards,

    Anand

Reply
  • in reply to amrao

    Hello,

    I have an update on this issue. Our digital designer was able to convert the VHDL block to a Verilog block. I now

    take a different approach where I import all the blocks to create Functional views and then point the top level digital

    block to use the functional view instead of including all the files as before. This brings the entire digital hierarchy into

    the Config view.

    Now the AMS simulation runs with all Verilog blocks but still fails when I try to use the VHDL view which is imported as an 'rtl'

    view. The error in the simulation log file is just 'failed to compile module' for the VHDL block. A screen capture of the logfile

    utility is attached below. 

    Logfile Utility

    We would still like to be able to use both Verilog and VHDL views since there is a mix allowed for the project.

    Best Regards,

    Anand

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