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FATAL: The following branches form a loop of rigid branches (shorts) when added to the circuit

bikram94

Hello,

I am getting fatal errors at the time of the simulation. 

Using Verilog-A view only.

Please help to debug these issues.

====Errors:====

Notice from spectre during initial setup.
Ignorevaref=yes is ignored since all nodes are connected to Verilog-A modules.
Fatal error found by spectre during topology check.
FATAL: The following branches form a loop of rigid branches (shorts) when added to the circuit:
I1:prefout2_flow (from prefout to 0)
I1:pdetout2_flow (from pdetout to 0)

========

test bench

Verilog-A code 

=====================================================

// VerilogA for  test_bias, veriloga

`include "constants.vams"
`include "disciplines.vams"
`define L(pin) (V(pin,vss)>V(vdd,vss)/2)

module test_bias(en_bias,iout,en_pdet_out_bias,en_pref_out_bias,vdd,vss,pdetout,prefout);

input en_bias;
electrical en_bias;
inout iout;
electrical iout;
inout en_pdet_out_bias;
electrical en_pdet_out_bias;
inout en_pref_out_bias;
electrical en_pref_out_bias;
inout vdd;
electrical vdd;
inout vss;
electrical vss;
inout pdetout;
electrical pdetout;
inout prefout;
electrical prefout;

analog begin

if(`L(en_bias)==1) begin
I(vdd,iout) <+ 10e-6;
end
else begin
I(vdd,iout) <+ 0;
end

if(`L(en_pdet_out_bias)==1) begin
V(pdetout) <+ 0.5;
end
else begin
I(pdetout,vss) <+ V(pdetout,vss)*1e-12;
end

if(`L(en_pref_out_bias)==1) begin
V(prefout) <+ 0.5;
end
else begin
I(prefout,vss) <+ V(prefout,vss)*1e-12;
end


end

endmodule

==================================================

===================================================

// VerilogA for test_bias2, veriloga

`include "constants.vams"
`include "disciplines.vams"
`define L(pin) (V(pin,vss)>V(vdd,vss)/2)

module test_bias2(en_bias2,iout2,iout_in,en_pdet_out_bias2,en_pref_out_bias2,vdd,vss,pdetout2,prefout2,in_sig,out_sig);

input en_bias2;
electrical en_bias2;
inout iout_in;
electrical iout_in;
inout iout2;
electrical iout2;
inout en_pdet_out_bias2;
electrical en_pdet_out_bias2;
inout en_pref_out_bias2;
electrical en_pref_out_bias2;
inout vdd;
electrical vdd;
inout vss;
electrical vss;
inout pdetout2;
electrical pdetout2;
inout prefout2;
electrical prefout2;
input in_sig;
electrical in_sig;
inout out_sig;
electrical out_sig;

analog begin

if(`L(en_bias2)==1) begin
I(iout2) <+ I(iout_in);
V(out_sig) <+ V(in_sig);
end
else begin
I(iout2) <+ 0;
V(out_sig) <+ 0;
end

if(`L(en_pdet_out_bias2)==1) begin
V(pdetout2) <+ 0.5;
end
else begin
I(pdetout2,vss) <+ V(pdetout2,vss)*1e-12;
end

if(`L(en_pref_out_bias2)==1) begin
V(prefout2) <+ 0.5;
end
else begin
I(prefout2,vss) <+ V(prefout2,vss)*1e-12;
end

end

endmodule

===================================================

Parents

  • You potentially have (two sets of) two voltage sources in parallel V(pdetout) from the first model and V(pdetout2) from the second model, and the same for V(prefout)/V(prefout2). Maybe you've carefully arranged the "bias" signals to prevent them both being connected at the same time, in which case you might be able to solve this by adding (* no_rigid_switch_branch *) immediately before the word "analog" in "analog begin". Be aware though, that this simply prevents the check - if there genuinely is a loop of voltage sources, then you'll end up with a convergence failure.

    Another approach could be to add a small impedance (no smaller than 1mOhm though, as it's not a good idea to have very tiny resistances; this can affect convergence) at the outputs of the block as this would prevent the loop.

    Regards,

    Andrew

Reply

  • You potentially have (two sets of) two voltage sources in parallel V(pdetout) from the first model and V(pdetout2) from the second model, and the same for V(prefout)/V(prefout2). Maybe you've carefully arranged the "bias" signals to prevent them both being connected at the same time, in which case you might be able to solve this by adding (* no_rigid_switch_branch *) immediately before the word "analog" in "analog begin". Be aware though, that this simply prevents the check - if there genuinely is a loop of voltage sources, then you'll end up with a convergence failure.

    Another approach could be to add a small impedance (no smaller than 1mOhm though, as it's not a good idea to have very tiny resistances; this can affect convergence) at the outputs of the block as this would prevent the loop.

    Regards,

    Andrew

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