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  3. Transient stop time for specified number of clocks

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Transient stop time for specified number of clocks

Senan
Senan over 4 years ago

Hello,

I am optimizing a variable clock signal generator circuit by changing the circuit parameters in Cadence Virtuoso. I am running the transient simulation and calculating the generated signal frequency.

During the optimization, the generated clock frequency is varying in very wide range (from 50 kHz to 20 MHz), if I fix the "Stop Time" in the transient simulation to cover the low frequency signals, then the simulator will consume huge time to complete the high frequency signals. 

what is perfect for me is to watch five periods of the generated clock regardless its frequency, which means I need dynamic Stop Time , but I don't know how to define this condition as a variable in formula form in the stop time.

Thank you

Best Regards

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  • Andrew Beckett
    Andrew Beckett over 4 years ago

    Assuming you can create a variable called TSTOP (say) which is a function of other variables to compute the stop time, put VAR("TSTOP") in the transient stop time field.

    Andrew

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  • Senan
    Senan over 4 years ago in reply to Andrew Beckett

    Dear Andrew,

    Thanks for your reply, that was useful, but is there a function in Cadence to make TSTOP variable  equal to 10 periods?, where the period is from the output generated signal.

    Thanks

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  • ShawnLogan
    ShawnLogan over 4 years ago in reply to Senan

    Dear Senan,

    I do this all the time. Here are a few steps that I hope may help.

    1. Define the frequency of your pulse generator and use this variable to set its frequency, for example freq_MHz.

    2. Define a variable containing the number of periods you want to simulate the pulse generator, for example, num_periods

    3. Define a variable, tstop, to contain the end time of your simulation as:

    tstop = numperiods/(1e6*freq_MHz)

    4. In the transient simulation set up GUI, indicate the stop time of your simulation as;

    VAR("tstop")

    I hope I understood your question correctly Senan and this suggestion helps provide you some insight!

    Shawn

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  • Senan
    Senan over 4 years ago in reply to ShawnLogan

    Dear Andrew and Shawn

    Thanks alot for your reply

    Indeed this setting I usually use in my all transient simulation, my case in this post is little different and I am sorry if I fail to make it clear,

    in yours and Andrew solutions, you are assuming that I know the value of the generated frequency or at least approximated value, while my circuit is a little bit crazy, it has many variables for optimization purposes and during the optimization process different clock frequencies are presented in the output with abroad difference (can give fck between 50 kHz and 12 MHz).

    If I would now set the stop time to cover the longer period (50 kHz), the simulation will take huge time if the generated signal is 12 MHz,

    So in short, freq is unknown, and with this abroad difference in the generated signal, I can not choose an average value.

    I have tried one thing but didn't work, I used the same formula you gave me (tstop = numperiods/(1e6*freq_out)), and instead I give the value of of freq_out by me, I used the cadence calculator to exctract the clock frequency from the output generated signal, but sure it was not accepted 

    Thank you once again

    Regards

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  • Andrew Beckett
    Andrew Beckett over 4 years ago in reply to Senan

    You can't set the stop time to be a calculator function of the output from the current simulation - you have a "chicken and egg" situation - you can't find the frequency until the simulation has finished, and once finished, the stop time would have no effect. 

    You could use a Verilog-A model in your test bench to count the output pulses and then use $finish_current_analysis to end the transient at that point - and set the transient stop time to be the worst expected stop time. The Verilog-A code would then cause the transient to stop early.

    Andrew.

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  • Senan
    Senan over 4 years ago in reply to Andrew Beckett

    Dear Andrew,

    That is a perfect answer to my situation, exactly what I neeed

    one relevant question please, do you mean that I will put $finish_current_analysis in the counter Verilog model?

    Thank you

    Regards

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  • Andrew Beckett
    Andrew Beckett over 4 years ago in reply to Senan

    I'm assuming you have a Verilog-A model which is connected to the pulse output which counts the number of pulses, and when the desired count is reached, it calls $finish_current_analysis - in the same model.

    Andrew

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