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  3. How Can I Pass a Variable-sized Array to an Analog User...

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How Can I Pass a Variable-sized Array to an Analog User-defined Function in VerilogA?

rhanna
rhanna over 4 years ago

Hi,

I need to pass an input array to an analog user-defined function that has a size controlled by a certain parameter. Is that feasible in VerilogA?

e.g. 
...
Parameter integer n = 10;
Parameter real x [0:n-1];
Parameter real y;
real dummy;
...
analog function real func;
          input x_,n_;
          output y_;
          integer n_ = 10;
          real x_ [0:n-1], y;
...
endfunction

analog begin
...
          dummy = func(x,n,y);
...
end

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  • Andrew Beckett
    Andrew Beckett over 4 years ago

    This is not possible in Spectre or AMS Designer. It's slightly ambiguous in the Verilog-AMS LRM as to whether it is allowed or not.

    Certainly you can do this (this arrayadd example is from the LRM, and works in Spectre):

    `include "disciplines.vams"
    module forumarray (n1,n2);
    
    output n1,n2;
    electrical n1,n2;
    real a1[0:1]={5,3},b2[0:1]={3,4};
    
      analog function real arrayadd; inout [0:1]a;
        input [0:1]b;
        real a[0:1], b[0:1]; 
        integer i;
        begin
          for(i = 0; i < 2; i = i + 1) begin
            a[i] = a[i] + b[i];
          end 
        end
      endfunction
    
    analog begin
    
      @(initial_step) arrayadd(a1,b2);
    
      V(n1) <+ a1[0];
      V(n2) <+ a1[1];
    
    end
    
    endmodule
    
    

    However, if you change the function to be this (note, the errors were less clear if I used n-1 so I simplified to just use a direct parameter; as a result, the array is one wider than it needs to be):

    `include "disciplines.vams"
    module forumarray (n1,n2);
    
    output n1,n2;
    electrical n1,n2;
    real a1[0:1]={5,3},b2[0:1]={3,4};
    
      analog function real arrayadd;
        input n;
        inout [0:n]a;
        input [0:n]b;
        real a[0:n], b[0:n]; 
        integer n;
        integer i;
        begin
          for(i = 0; i <= n; i = i + 1) begin
            a[i] = a[i] + b[i];
          end 
        end
      endfunction
    
    analog begin
    
      @(initial_step) arrayadd(1,a1,b2);
    
      V(n1) <+ a1[0];
      V(n2) <+ a1[1];
    
    end
    
    endmodule
    

    then it fails with errors:

    Error found by spectre during AHDL read-in.
        ERROR (VACOMP-1579): "inout [0:n]<<--? a;"
            "forum122a.va", line 10: Encountered a range value that is not an integer or a real. Specify a numeric expression.
        ERROR (VACOMP-1579): "input [0:n]<<--? b;"
            "forum122a.va", line 11: Encountered a range value that is not an integer or a real. Specify a numeric expression.
        ERROR (VACOMP-1579): "real a[0:n]<<--? , b[0:n]; "
            "forum122a.va", line 12: Encountered a range value that is not an integer or a real. Specify a numeric expression.
        ERROR (VACOMP-1700): "forum122a.va", line 12: Encountered one or more array bounds that are not constant integer expressions. Use constant integer expressions to specify the array bounds.
        ERROR (VACOMP-1579): "forum122a.va", line 12: Encountered a range value that is not an integer or a real. Specify a numeric expression.
        ERROR (VACOMP-1700): "forum122a.va", line 12: Encountered one or more array bounds that are not constant integer expressions. Use constant integer expressions to specify the array bounds.

    I've not found any requests for this - but it's quite difficult to search for. Perhaps you should contact customer support.

    I checked too with Verilog-AMS, but that hits a more fundamental problem that inout arguments (and output too) are not supported in analog functions. There's a change request for that, CCR 1298797, but it's not been implemented (I think the reason is that Verilog doesn't (or at least didn't - I've not re-checked against the latest Verilog standard) support this.

    Regards,

    Andrew

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