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Changing range of sweep in DC analysis leads to different results

Qihang H

Hi there,

I'm building a two-stage fully differential amp and I try to find the proper DC operating point, so I swept the width of the PMOS on the most top of first stage(i noted in the pic) and looked at the output node DC voltage of first stage.(I want to have around 800mV) First I did the sweep in 0.6u - 1.1u range, then I did it again in 0.7u - 1.1u range, the graphs are totally different! Even the width value appears in both graphs has different voltage results.

Did anyone deal with a similar problem before? I'm a newbie so the problem may be quite stupid, but any advice will help!

Thanks a lot!

Qihang

  • in reply to Qihang H

    Dear Qihang,

    Qihang H said:
     I added a common-mode feedback structure to sample the output common-mode voltage and feedback to vbias3. It seems to act quite well, at least I got a proper DC point and 67dB gain. Although the bandwidth and phase margin are not really satisfying but I believe I can make it.

    Excellent! I am happy to read this!

    Qihang H said:
    2. It should be, but I'm not 100% sure. My understanding is the load capacitance represents everything connected to the output in the real circuit. It could be e.g. multiple comparators in a flash ADC. I'll consider the load capacitance and try to optimize the AC performance.

    Yes. I am concerned that a 1 pf load capacitance may be too much and result in poor phase margin.

    Qihang H said:
    . I didn't manually set the DC operating point of output stage. Do you mean the common-mode feedback part

    Yes. The common-mode feedback was what I was referring to and I believe you have now added that.

    Good luck Qihang!

    Shawn

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