Changing range of sweep in DC analysis leads to different results

Dear Qihang,

Qihang H said:

First I did the sweep in 0.6u - 1.1u range, then I did it again in 0.7u - 1.1u range, the graphs are totally different! Even the width value appears in both graphs has different voltage results.

I suspect, with the topology of your circuit and the number of stacked transistors, you have more than one valid operating point and hence your two simulation results are different. Are you sure this is not the case?

Shawn

Dear Shawn,

Thanks for the reply, Do you mean there might be multiple width values leading to the same voltage? It's possible, but to make all devices in the telescopic cascode branch saturated, the voltage of that node should be at least in the range of 700-900mV in my condition. My supply is 1.5V and the technology is GF28nm.

As I set the width to about 0.96u(it should correspond to about 800mV in my first sweep) and run the DC simulation without sweeping, it turns out to have the value in the second sweep(1.3V). I wonder if there are two valid width values, doesn't that mean both values can result in a similar voltage around 800mV?

Qihang

Dear Qihang,

> Do you mean there might be multiple width
> values leading to the same voltage?

I am sorry to have confused you Qihang!

Basically, it is possible with the circuit topology you are using that for the same device sizes, there are more than one DC operating points that are stable. With a DC sweep, the operating point that spectre computes can depend on the direction of the sweep or, in your case, changes in device width. Note for some of the widths you selected, the two DC operating points are the same - which suggests the multiple stable operating points may just occur for some device widths

> ....doesn't that mean both values can result in a
> similar voltage around 800mV?

This is exactly what I tried to express, but in terms of voltage. Yes, having two different widths could lead to a similar voltage.

To explore the existence of multiple operating states, you might consider running a transient simulation where you ramp the supply voltage at different rates (i. e., change the slope/rise time) and examine the final DC voltages in the circuit as this can often reveal the presence of multiple stable operating points.

The use of a transient simulation to study this does not guarantee there are not multiple operating points that are stable, but is simply a way to possibly reveal them.

I hope this clarifies my prior response that was confusing to you!

Shawn

Dear Shawn,

Thank you for the detailed explanation!

I set the slope of my input common-mode voltage to different values then plot Vin,cm and DC voltage of output node. It turned out to have two regions where the voltage is relatively stable(around 1V and 500+mV). I also did the same thing to VDD and the curve is as follows. Output DC voltage ends up at 300mV which is not the same value as in the former picture. I assume in this case I do have two different DC operating points.

Could you please tell me what can I do to get about 800mV for the output DC voltage? I'm not sure if I should adjust the device widths or the bias voltage for cascode device. It's actually my first project. Thanks again for the advice!

Qihang

Dear Qihang,

Qihang H said:

It turned out to have two regions where the voltage is relatively stable(around 1V and 500+mV). I also did the same thing to VDD and the curve is as follows. Output DC voltage ends up at 300mV which is not the same value as in the former picture. I assume in this case I do have two different DC operating points.

Yes - I am very happy to read you were able to determine this! Great!

Qihang H said:

Could you please tell me what can I do to get about 800mV for the output DC voltage? I'm not sure if I should adjust the device widths or the bias voltage for cascode device. It's actually my first project.

I'm not sure if it is appropriate if this is for an exam or private work project. There are many references available on differential amplifiers, cascode structures, and design issues (such as headroom). Do you think it is appropriate in lieu of you researching this?

Shawn

Dear Shawn,

Thank you for all the things you have done!

You are right, it's a project from my university and I should come over with all the problems alone.

I actually searched a bunch of papers and went through several books, they mainly focused on the principle and topologies (like to slightly increase the headroom you can use folded cascode instead of telescopic). I used the gm/id methodology and determined all device sizes from the specs, but when I put all the numbers into Virtuoso, it didn't work exactly as I calculated (I know it's not supposed to be, because my calculation with square law model is not really accurate). Then I started to confuse how can I adjust the circuit to push it into the DC operating point I want? I did it by changing the device widths and observe the nodal voltage. It's basically qualitative, I just made a random change and see if the nodal voltage increased or decreased.

The "DC operating point adjustment" part actually never shows up in papers. May I ask you for a little guidance on how people do the adjustment when designing e.g. an amplifier in a project? (Is it right to change the device width after the overdrive voltage assigned?) A general idea is enough. I really appreciate it and sorry for the long reply.

Qihang

Dear Qihang,

Qihang H said:

You are right, it's a project from my university and I should come over with all the problems alone.

and

Qihang H said:

A general idea is enough.

Thank you for being honest about your need for an answer to your question! I understand and am certainly willing to provide some guidance. Your integrity is admirable!

Qihang H said:

I'm not sure if I should adjust the device widths or the bias voltage for cascode device.

A few items to consider first Qihang...

1, As shown in Figure 1 where I annotate the circuit diagram you provided in your post, I believe the bias conditions you have set up for your differential pair N1 and N2 do not provide for any gain since they are not biased in the their saturated regions. If the gate voltages of N1 and N2 are 0.0 V (as its appears your schematic indicates), then for them to be in saturation, their gate-source voltages must be greater than their threshold voltages - let's say 500 mV. Hence, their common soruce terminals would be at -500 mV. However, if the drain of No connected to their common source terminal is at -500 mV, it cannot be acting as a current source as the source of N0 is at 0 V. This means the current through your differential pair N1 and N2 is close to 0 and hence it has no significant voltage gain. You need to set the source of N0 to a negative voltage power supply or, alternately, set the gates of N1 and N2 to a DC bias voltage of at LEAST their DC threshold voltage and preferably higher than that to allow N1 and N2 to work as a differential pair. This is of prime importance and needs to be corrected before you consider optimizing the device widths to get your desired output voltage.

2. If this is your first project, I might also suggest you not choose the differentiar pair's load to a complex circuit such as a cascode - it might be more instructive and intuitive to you if you set the output load to a non-cascoded current source.

3. In your circuit, it appears that P0 and P2 are not required. Is there a reason you have included them? The only potential reason you might need them might be as devices to enable a power-down function. Once again, if this is your first project, consider eliminating devices P0 and P2, replace devices P1, P3, N3 and N4 with a basic current source and then adjust the DC bias voltages to N1 and N2 to make sure your differential pair is operating with some gain.

4. If you decide to consider my suggestions in [3], then consider adjusting their bias points (or device widths/lengths) to place your second gain stage, formed by P10, in its gain region.

Shawn

Figure 1

Dear Shawn,

Thank you for your instruction! I'm sorry for the late reply, my computer was not available for the last few days.

Unknown said:

1, As shown in Figure 1 where I annotate the circuit diagram you provided in your post, I believe the bias conditions you have set up for your differential pair N1 and N2 do not provide for any gain since they are not biased in the their saturated regions.

Sorry to confuse you with that! I'll post a screenshot with all DC operating points below. First I tried to disconnect the second stage from the first and just adjust the first stage, and I did it. It acts very smoothly with a 40+dB gain. Then I added the second stage and Miller compensation into the schematic and the DC operating points changed. Then that problem I told you before appeared: I tried to fix all the biasing voltage(because they are proper when I just simulate the first stage) and tune the size of devices to get again a good DC operating point, but I can't really get it. Now I know that I have two valid DC operating points thanks to your advice.

Unknown said:

In your circuit, it appears that P0 and P2 are not required. Is there a reason you have included them?

I read from Razavi book that if adding P0 and P2, the output impedance of the whole amplifier would be more "balanced", i.e. the output impedance is the impedance at the output node looking up in parallel with it looking down. If using a NMOS cascode structure and a simple PMOS pair load, the output impedance would be basically up to the PMOS impedance(they are smaller in parallel). I want to achieve a better performance, but indeed you are right, if I use simple PMOS pair it would be much easier to tune the circuit.

Just the first stage:

Sorry I have to cut them into two pictures because my monitor is not big enough to make all the numbers clear.^^ As you can see in the pictures, I deleted the connection between first and second stage. When just regarding the first stage, it was quite good and all devices were saturated.

But when repeat it by two-stages, it became suddenly difficult to find a proper DC operating point. I believe the gate voltage of the second stage (P10, P11) is too high so that they are off. And I have to adjust the widths of P0 and P2 again to achieve that.

I will try to analyze the transient analysis to know more about the two DCop points, thanks for your advice again!

Best regards,

Qihang

Dear Qihang,

Qihang H said:

When just regarding the first stage, it was quite good and all devices were saturated.

Yes. The DC operating points you are showing in an annotated version I created and show as Figure 2 appear quite reasonable. The devices N0 - N4 appear to be in their saturated regions of operation. However, as you mentioned, you have disconnected the output stage from this differential stage. As a result, you do not have any feedback between the differential input nodes shown as vin+ and vin- and the output of stage 1. Therefore, the stage is operating in open loop mode.

Qihang H said:

But when repeat it by two-stages, it became suddenly difficult to find a proper DC operating point. I believe the gate voltage of the second stage (P10, P11) is too high so that they are off. And I have to adjust the widths of P0 and P2 again to achieve that.

I believe you have now added too much gain with the second stage (and no feedback between the input and output nodes) as the only output load may be current source output impedances that are biased off. Please see my questions in the annotated version of your second recent posts figure.  With such a high open-loop gain, even a very tiny numerical error between vin+ and vin- may result in an output pegged at a supply - and it appears pegged at ground. Even if you connect the outputs somehow to the inputs, I am concerned you have loaded the output with too high a capacitance (1 pf). Too high a capacitance can result in instability.

Shawn

Dear Shawn,

Thank you! You have inspired me about the stability of the open-loop circuits. I added a common-mode feedback structure to sample the output common-mode voltage and feedback to vbias3. It seems to act quite well, at least I got a proper DC point and 67dB gain. Although the bandwidth and phase margin are not really satisfying but I believe I can make it. Thank you again for everything!

1. I didn't add any feedback before, thought I could tune everything in open-loop first and then add the feedback so that I can make sure which part went wrong if it didn't work. I think the truth is you can't really separate the amplifier stage and feedback stage as the operating condition changes totally .

2. It should be, but I'm not 100% sure. My understanding is the load capacitance represents everything connected to the output in the real circuit. It could be e.g. multiple comparators in a flash ADC. I'll consider the load capacitance and try to optimize the AC performance.

3. I didn't manually set the DC operating point of output stage. Do you mean the common-mode feedback part? I don't even know we have to set that for a common source stage. Does it mean we have to connect somehow a voltage source to the output?

Qihang