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Stability Analysis Issue on Schematic level

GirishW over 4 years ago

Stability Analysis Issue on Schematic

Hi There,

I am trying to run stb analysis on schematic level (pre-layout). Breaking loop with metal resistor at one level inside

(using IC6.1.8.64b.500.17) and ( cadence Explorer)

Following this article -

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000tt0rEAA

This schematic is one level down in hierarchy >> TOP schematic >> loop schematic

I did verify from netlist -

I did try using name of net name ("name of top schematic"\"name of net") in deepprobe . But, It does not work.

Problem - I can see from simulation results that, loop is broken at DC analysis and voltage on one node is 1.62V and another node is 0V. So it means that, feedback loop is broken in DC analysis

Parents

Frank Wiedmann over 4 years ago

You need to specify the instance name of the top schematic in front of the net name. If the instance name is I0, the node names in the deepprobe components should be I0.net3 and I0.net4. Note that the separator is the dot (.), not the backslash (\).
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GirishW over 4 years ago in reply to Frank Wiedmann

Hi Frank,

Thank You very much for reply. It worked. I really appreciate your help and your articles of loop gain on site.google are always helpful.
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GirishW over 4 years ago in reply to Frank Wiedmann

Hi Frank,

Thank You very much for reply. It worked. I really appreciate your help and your articles of loop gain on site.google are always helpful.
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