Update VerilogA outputs during simulation based on values read from from

For verification of an analog block, I am trying to set up my testbench such that I can change the output of a verilogA input stimulus during transient simulation. The goal is to read a text file at every rising edge of a clock and use the value to change the behaviour of the analog block. The text file will contain only a single line with a single integer value. The version of Spectre is 20.10.isr3

In Spectre X simulation log, I see the CSV file, PGA_GAIN_DATA, being read at the first crossing event with the message "Reading file: /home/c99485/simulation/sandbox/sandbox/maestro/results/maestro/PGA/netlist/PGA_GAIN_DATA.txt". the output bus of the verilogA was also updated. However, all subsequent crossing event did not yield any other messages and it appear that Spectre simulator would just reuse the data that it had acquire from the first read and stored in its memory. Removing or renaming the file after the first instance did not affect the transient simulation. 

Is this behaviour expecter? Can I get Spectre to re-read the CSV file and not reuse the data from its memory? 

==========

// VerilogA for sandbox02, CTRL_PGA, veriloga

`include "constants.vams"
`include "disciplines.vams"

module CTRL_PGA (VDD, VSS, PGA_GAIN, CLK);

  output [3:0] PGA_GAIN;
  inout VDD, VSS;
  input CLK;

  electrical [3:0] PGA_GAIN;
  electrical VDD, VSS, CLK;

  integer OVR_PGA_GAIN;
  integer fileID, retval;
  real vthres;
  genvar i;

  analog begin

      @(initial_step) begin
         vthres = V(VDD)-V(VSS);
         OVR_PGA_GAIN = 0;
      end

     @(cross(V(CLK) - vthres, 1.0)) begin
        fileID = $fopen("PGA_GAIN_DATA.txt", "r");
        if (fileID > 0) begin
          retval =1;
          while (retval == 1) begin
          retval = $fscanf(fileID, "%d", OVR_PGA_GAIN);
        end
      end
    end

    for (i=3; i>=0; i=i-1) begin
      V(PGA_GAIN[i]) <+ (OVR_PGA_GAIN>>i)&1 ? V(VDD) : V(VSS);
    end

  end
endmodule