Simulation of gate leakage current using cadence

Dear Minghao,

I don't think I fully understand your simulation. What are the drain, bulk, and source nodes connected to during your DC and transient simulations? What temperature are you running your simulations? What is the range of the DC gate voltage you are applying? What is the size of your device under test and is it an IO or core device?

Each of these can impact the amount of Gaye leakage you might observe.

Shawn

Thank you ShawnLogan

The drain, bulk, source are all connected to the ground. I apply a 2V DC voltage to the gate of a NMOS (model name is nmos2v in TSMC 180nm process, W/L=2/2). All simulation are under room temperature.

For all simulation I run before, the Ig shows NaN and other sub-current like Igd, Ige, Igb shows exactly zero.

I'm looking for your reply!

Minghao

Dear Minghao,

Minghao said:

The drain, bulk, source are all connected to the ground. I apply a 2V DC voltage to the gate of a NMOS (model name is nmos2v in TSMC 180nm process, W/L=2/2). All simulation are under room temperature.

For all simulation I run before, the Ig shows NaN and other sub-current like Igd, Ige, Igb shows exactly zero.

My guess is the nmos2V model is likely an I/O device (as opposed to a core voltage based device) and hence has both a significant threshold voltage as well as a thick gate oxide. As a result, its gate leakage current is negligible. Therefore, an attempt to determine its value in simulations will show a near zero value.

As potential validation of this hypothesis, I created a test bench using two different types of 5 nm 1.2 V based nmos I/O devices and simulated their gate leakagesas a function of the gate voltage. I configured the devices in the same fashion as your test bench with the gate terminal connected to the DC supply and source, drain, and bulk nodes set to ground. I swept the gate voltage and found that both gates show either 0.0 leakage current for nearly all gate voltages except for a one voltage where it was on the order of 1e-36 A. Hence, I would not be surprised if a 2V, 180 nm device shows a similarly negligible gate current.

Significant gate leakage currents due to tunneling and thin oxide effects can be significant in more advanced technology nodes (<< 180 nm) in their core voltage threshold device offerings.

I hope this provides some insight into your simulation results Minghao!

Shawn

P.S.  Since I do not have immediate access to the 180 nm technology PDK you are using, I cannot absolutely confirm my hypothesis.