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Generating Liberty (.lib) File From Verilog-A Table Model

Hello,

I want to create a liberty file for a new technology that I have access to verliog-A table model using Cadence Liberate. I can't find any guidance in the Liberate documents. Is it possible to use the Verilog-A model instead of the Spice model to create a liberty file using Cadence Liberate? Can anyone help me with how I can do that?

Many Thanks

Guangjun Cao over 4 years ago

I have never heard of using Verilog-A model in Liberate. But you may try similar approach for hdl model. in the reference manual, go to define_leafcell section, example-2.
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kainlulk123 over 3 years ago in reply to Guangjun Cao

Recently, I have similar need and found this in another thread: https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/42194/characterizing-library-for-emerging-2dfets-with-in-house-va-based-models.
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Guangjun Cao over 3 years ago in reply to kainlulk123

Hi kainlulk123,

Do you find the linked thread helpful?

if you still have an issue, please start a new thread.

Thanks,

Guangjun
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