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skipping digital registers in analog extracted simulations

Mohamayreh

Hallo, 

I would like to simulate my design after layout. My design consists of a big analog part and a lot of shift registers that are used to configure the analog part.

Now I finished the layout of all components including analog and registers together. When performing analog extracted using quantus of the top level I can not longer configure the value of the registers since I can no longer set the cell view to veriloga in the config. Therefore I can only simulate the system with registers have a value of zero. 

Is there is a way to generated an analog extracted view without flattening the registers as well.

Thanks and regards

Mohammad

  • ShawnLogan

    Dear Mohammed,

    Mohamayreh said:
    Is there is a way to generated an analog extracted view without flattening the registers as well.

    I'm not sure I fully understand how you set your registers if there are no external pins to them. However, I might suggest that you consider black boxing all the digital logic and then you can include a view within the extracted view for the block. Of course, you will LOSE all potential coupling and interaction issues between the two and this may not be acceptable . It is not uncommon to have coupling issues as a result of digital logic traces within an analog block.

    Shawn

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