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Liberate AMS GUI: arc present in log file, but not generated in .lib file

stagro

Liberate AMS GUI: arc present in log file, but not generated in .lib file


Hello,
I am using dynamic arc generation, Liberate AMS GUI.
I have problem that my two arcs, which are defined in Define Arcs tab are present in log file, with correct value compare to simulation, but these two arcs are missing in generated .lib file.

The log file shows this:


(AMS-info) - for arc:
  define_arc -type DELAY
    -when RST_A_B_1V8&!SM_1V8&ENA_1V8&!INTEST_1V8<6>&!INTEST_1V8<5>&COL_1V8<0>
    -pin BIT_O_1V8
    -pin_dir R
    -related_pin ROW_1V8<0>
    -related_pin_dir R
    -value {3.757736305e-08 }

  TABLE LINE(s): 30
  TABLE TIME(s): 1.550000000e-06 s
            -rel ROW_1V8<0> could not be reached in dynamic traversal
            This either means that chosen arc is false, activity information from fastsim is missing/improper or arc spans multiple clock cycles
            Please check table /proj/mem_onc18gen2_onipp_lv/workareas/fg87vf/liberate_ams/mem_onc18gen2_onipp_lv_sg_mem_onc18gen2_onipp_lv_16x16_schematic/C0/ams_reuse/ams_decks/tran.scs.timing.tbl at line: 30
            Trying to automatically recover ...

(AMS-info) - for arc:
  define_arc -type DELAY
    -when RST_A_B_1V8&!SM_1V8&ENA_1V8&!INTEST_1V8<6>&!INTEST_1V8<5>&COL_1V8<0>
    -pin BIT_O_1V8
    -pin_dir R
    -related_pin ROW_1V8<0>
    -related_pin_dir R
    -value {3.757736305e-08 }

  TABLE LINE(s): 30
  TABLE TIME(s): 1.550000000e-06 s
            -rel ROW_1V8<0> could not be reached in dynamic traversal
            This either means that chosen arc is false, activity information from fastsim is missing/improper or arc spans multiple clock cycles
            Please check table /proj/mem_onc18gen2_onipp_lv/workareas/fg87vf/liberate_ams/mem_onc18gen2_onipp_lv_sg_mem_onc18gen2_onipp_lv_16x16_schematic/C0/ams_reuse/ams_decks/tran.scs.timing.tbl at line: 28
            Trying to automatically recover ...
            ... could not recover; corresponding partition will be discarded and arc may be missing from final library

The same message is for the second arc.

Could anyone help what could be the cause of this error?

Parents

  • Would static mode work with your design?

    The message basically says the simulated waveform does not meet the expectation (s). You can check the simulation results at the time points according to the messages , is. Table/line.

    In most cases, you will need to use customer support with an full test case for an issue with liberate_ams.

    Regards,

    Guangjun

  • in reply to Guangjun Cao

    I am using static mode for a cell. There is a clk path CKIN -> CKOUT with only inverters in the path and a mux at the output stage - only a combinational path. ams.info file has the arcs defined for both CKIN (R) -> CKOUT (R) and CKIN (F) -> CKOUT (F). Now R->R is available in the .lib, but F->F arc goes missing in the *.rpt files and .lib file. How to go about debugging this?

Reply
  • in reply to Guangjun Cao

    I am using static mode for a cell. There is a clk path CKIN -> CKOUT with only inverters in the path and a mux at the output stage - only a combinational path. ams.info file has the arcs defined for both CKIN (R) -> CKOUT (R) and CKIN (F) -> CKOUT (F). Now R->R is available in the .lib, but F->F arc goes missing in the *.rpt files and .lib file. How to go about debugging this?

Children
  • in reply to RakeshDama

    Hi RakeshDama,

    Please do not post your question in an existing thread in the future.

    For your static run, please try this first, set_var static_prop_mode 1, using the latest Liberate release. If this does not work, you need to use SpiceVision tool to check the partitions. Alternatively, please contact customer service with a full test case. 

    From your description of the block, it may be easily handled by Liberate, as the size of cell does not sound very big. 

    Regards,

    Guangjun

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