veriloga output

Dear greywanderer,

I performed a comparative study of your veriloga comparator with that of the comparator veriloga model supplied by Cadence in its ahdl library and documented the results in the attached read-only PowerPoint file. I found the response of your comparator appears consistent with your veriioga code. I do not know our simulator, its version, or the specific transient simulation settings you used, but suspect perhaps your accuracy settings may not be sufficient to provide the kind of accuracy you are attempting to view. To avoid this situation, I ran the simulation with an errpreset of "conservative" and set a value of parameter "maxstep". The latter is likely not required, but I did decide to include it. The simulation settings and spectre/MMSIM versions I used are in the document as well as the test bench and simulation results.

Let me know if you have any thoughts or any trouble reading/opening the document....and I hope that I understood your concern sufficiently to provide a bit of additional information greywanderer!

Shawn

test_veriloga_comparators_v1p1_study_sml_100321c.pptx

The issue is that the signal is never above 500mV (the threshold) and so it doesn't cross 500mV. If the input starts exactly on the threshold, then the output is 0 and it doesn't change because doesn't cross the threshold. If you have your input signal start at 501mV and drop to 499.3mV then you would see the transition.

Andrew

Hi Andrew,

The yellow data point on the left of the vertical marker is around 530mV.

Here is the zoomed out version of the same plot.


Shawn,

I am using the conservative setting and these are the settings that the simulator is using for the transient,
reltol=100u
vabstol = 1uV
iabstol = 1pA

The simulation also uses APS(not ++aps)

The simulator details are,

Spectre (R) Circuit Simulator
Version 18.1.0.464.isr11 64bit -- 21 Sep 2019

I understand that tightening the maxstep can help but also have read other posts by Andrew that it might be unnecessarily conservative and the usage of the "cross" should allow the simulator to tighten the accuracy around that region.

Thanks much for taking a look.

OK, the original picture was not that clear (it still isn't). It's switching from your newer graph - what's the issue here? Note that there is a tolerance - the simulator is trying to solve for the crossing point and place a timepoint near to the crossing point (see the Verilog-A documentation on the cross function) and there are some expression tolerances (which would be reltol*maxValue which in this case would be (I think) 1e-4*2 - i.e. 0.2mV. So it's not guaranteed to have the crossing exactly at the crossing (it's a simulator - everything is done to a tolerance).

I don't think I entirely understand what your problem is though, since the graph in the post immediately above appears to be working OK.

Andrew

I got confused because the vabstol = 1uV. But I guess the simulator tries to meet max(reltol*maxValue, vabstol).

Thanks!