clock buffer chain jitter measurement under deterministic supply noise

Dear YutaoLiu,

There are similar questions in this Cadence Community post and its replies at URL:

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/43477/noise-jitter-transfer-function-along-clock-driven-inverter-chain

Did you happen to read this? It speaks to both your questions on the use of PSS/PXF and of your choice of using a sampled noise analysis.

Shawn

Hi Shawn,

Thanks for your reply.

I read this post you mentioned above just now. Although it also focus jitter in clock buffer chain, the power supply was DC. In my case, the power supply is sinusoidal, and its frequency is 1/80 of the clock frequency.

Thanks and regards,

Yutao

Dear YutaoLiu,

YutaoLiu said:

I read this post you mentioned above just now. Although it also focus jitter in clock buffer chain, the power supply was DC. In my case, the power supply is sinusoidal, and its frequency is 1/80 of the clock frequency.

in your original Forum post, you asked the question:

YutaoLiu said:

Could you point me to some material? I usually see material about PSS+PXF to measure transfer function from power supply to output.

I tried to suggest you read the Forum post at URL:

community.cadence.com/.../1365526

where it states:

"Sampled PXF or sampled PAC is the right way to examine the transfer functions. You can also try the parameter separatenoise=yes (I have never really used it), but this won't work if you also use pnoisemethod=fullspectrum.

I suggest that you also examine the jitter caused by power supply variations with a sampled PXF (or sampled PAC) analysis."

as possibly addressing the question I quoted from your Forum post. Did I misinterpret your question? I thought you wanted some type of using PXF to measure the transfer function, and I thought Frank's comment directly related to it...perhaps I misunderstood.

Shawn

Hi Shawn,

I am sorry that I confused you with my unclear statement in my post.

Actually I have two questions

1. Which should be the correct setting for beat frequency in PSS, 100MHz or 8GHz, when there is 100MHz 1mV sinusoidal signal on top of 0.75V DC at power supply, and clock signal is 8GHz? ?

2. If beat frequency is set as 100MHz in PSS, can PNOISE/PXF/PAC analyze jitter correctly? How should I set PNOISE or PXF/PAC with this beat frequency?

Thanks and regards,

Yutao

Dear YutaoLiu,

2. If beat frequency is set as 100MHz in PSS, can PNOISE/PXF/PAC analyze jitter correctly? How should I set PNOISE or PXF/PAC with this beat frequency?

> 1. Which should be the correct setting for beat frequency in PSS,
> 100MHz or 8GHz, when there is 100MHz 1mV sinusoidal signal on top of
> 0.75V DC at power supply, and clock signal is 8GHz? ?

The easy way to think about this question is to consider what a the pss convergence portion of a pss analysis is attempting to complete. The pss convergence portion of the analysis follows the tstab portion, where a near steady-state solution is hopefully achieved at the simulation time = tstab, and the pss convergence portion then attempts to determine a periodic waveform defined as a waveform whose final y-axis value is the same as its starting y-axis value.

If there is only a single frequency, f1, applied in the simulation, there is only one unique period that will satisfy this constraint and that is a period of 1/f1.

If there are, as an example, two different frequencies f1 and f2 in the simulated waveform, then in order to satisfy the pss convergence criteria, the minimum period over which the pss convergence phase will find a periodic solution is the first time interval which contains an integer number of periods of each waveform frequency f1 and f2. If f2 is an integer multiple of f1, f2 = N*f1, then the minimum time interval given by the period of f1. If the two frequencies are not integer related, say f2 = k*f1 where k is some non-integer value, then the minimum period over which the two waveforms will form a periodic waveform and satisfy the pss convergence criteria, is the least common multiple of the periods of f2 and f1. The frequency of the period representing the least common multiple of the periods is the "beat frequency" in a pss analysis. In your specific case, the least common multiple of the periods of 100 MHz and 8 GHz is 1/100 MHz or 10 ns.

A Microsoft Excel workbook I created to compute the least common multiple of two frequencies is at URL:

https://ent.box.com/s/aw3vgc2yzhhgpgrv1mtyil6s2ew72pw6

if you want to experiment with it.

(link to workbook expires 10/31/2021)

> 2. If beat frequency is set as 100MHz in PSS, can PNOISE/PXF/PAC
>  analyze jitter correctly? How should I set PNOISE or PXF/PAC with
>  this beat frequency?

Having written all this, you may not need to perform a pss analysis to compute the resulting time interval error or jitter. A simple conventional transient analysis or, if you want to study thermal noise as you mentioned, a transient noise analysis may suffice.

I happen to have a test bench with a series connection of CMOS inverters and have demonstrated the resulting time interval error of its output CMOS waveform using three methods and all agree. The test bench and the analysis results are at URL:

https://ent.box.com/s/226vhl2o56gxne1za52vy28kycqq1p5f

I also changed the analysis to a pss/pnoise analysis and provide those results as well. The latter simulation took much longer (19 minutes) than the conventional transient analysis (20+ seconds) with the pnoise simulation requiring the greatest percentage of simulation time.

(link expires in January 2022)

I hope this helps YutaoLiu,

Shawn

Hi Shawn,

Thank you so much for the detailed explanation.

Yes. I agree with you on the beat frequency setting.

I will try out your attach test bench setting.

Thanks again,

Yutao

Dear YutaoLiu,

I am happy to read you were able to access the links and found them somewhat helpful!! Thank you for letting me know too!

Good luck with your simulation. 

Shawn