Transient simulation termination by VerilogA model

Note: By mistake, I have posted this issue in the wrong forum and I am posting it here again

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Hello,

As I am simulating and optimizing a VCO circuit that generates a clock frequency with comprehensive change due to the optimization space, I fixed the stop time in the transient simulation to cover the lowest possible generated signal. While this time causes an unnecessary huge simulation time for the generated high-frequency signal, a method advised by this forum (by Andrew) to create a Verilog counter model shown below to count the pulses of the generated signal for a reasonable number of periods and the simulation module terminate the simulation regardless the signal frequency. Of course, the stop time in the transient simulation still needed to fit the lowest expected signal frequency. In this module, I am counting 10 periods which is more than enough to calculate the signal frequency using the function "frequency" from the calculator.

I have used the module in the transient simulation testbench and successfully terminate the simulation according to the predefined number of periods (count in this module). The ADE Assembler also was able to plot the signal after the simulation termination.

However, I have found that calculator functions results are not any more computed after termination, it becomes similar to the case when you manually stop the simulation and gives "sim error".

nevertheless, if I send the plotted signal to the calculator and apply the functions then it will work. but this will not solve my problem as I am running tens of corners and need to print the result automatically.

Kindly, I need your help to make the ADE Assembler compute the calculator functions automatically after simulation termination.

I am using Cadence Virtuoso IC6.1.8-64b.500.6

I hope I explained the problem clearly

Thank you in advance

Regards

####################################################################################Code'####################################################################################################

// VerilogA for indirect_measurement, counter, veriloga

`include "constants.vams"
`include "disciplines.vams"


`define SIZE 4
module counter (out, clk);
inout clk;
electrical clk;
output [`SIZE-1 :0] out;
electrical [`SIZE-1 :0] out;
parameter integer setval = 0 from [0:(1<<`SIZE)-1];
parameter real vtrans_clk = 0.6;
parameter real vtol = 0; // signal tolerance on the clk
parameter real ttol = 0; // time tolerance on the clk
parameter real vhigh = 1.2;
parameter real vlow = 0;
parameter real tdel = 30p;
parameter real trise = 30p;
parameter real tfall = 30p;
parameter integer up = 0 from [0:1]; //0=increasing 1=decreasing
parameter integer stepsize = 1;
integer outval;

integer cnt=0;

analog begin
@(initial_step("static","ac")) outval = setval;
@(cross(V(clk)-vtrans_clk,1,vtol,ttol))

begin
outval = (outval +(+up- !up)*stepsize)%(1<<`SIZE);

cnt=cnt+1;
if( cnt == 10) begin
   
            $finish(0);    //command to stop the current simulation
        end
end
generate j (`SIZE-1 , 0) begin
V(out[j]) <+ transition (!(!(outval &(1<<j)))*vhigh+!(outval&(1<<j))*vlow,tdel,trise,tfall);
end
end