Is it possible to do this in VerilogA?

Svilen,

No. You can have parts of the code enabled or not based on a compiler directive (e.g. `ifdef - see the "Controlling the Compiler" chapter of the Cadence Verilog-A Language Reference manual in the Spectre installation), but that's not a parameter. 

Why would you want to do this? 

Andrew

Thanks, Andrew, for replying. I have already looked at 'ifdef and it is not doing what I want.
OK, here is the long story. I have a verilogA block which does a search for a comparator offset and this part works fine. I wanted to use calcVal and take the offset from the offset search test and use it in another assembler test which performs pnoise simulation on the comparator. But it complains because of hidden states in the veilogA script. Funny thing is that I don't even need the  verilogA for the pnoise simulation, I just need  the result of it. But the verilogA block is in the test bench anyway. I tried also (*ignore_hidden_state*) but I still get the errors for the pss.

If the Verilog-A block is only generating an output (or only observing inputs) then you could mark the Verilog-A using the (* instrument_module *) attribute (Covered in the Verilog-A reference manual). However, it must not have inputs and outputs (i.e. the outputs must not depend on the inputs). It's not clear to me whether that's the case (not sure what "errors for the pss" you're talking about).

Note that you have to be careful when using such attributes as they can be an effective way of getting the wrong answer if misused.

Andrew

Yes, I tired also that attribute with no success. The verilogA block has as inputs the comparator output and the clock and the output is a voltage that goes and compensates the offset of the comparator, so at the end of the simulation that output is equal to the comparator offset itself. The whole thing works in a feedback.
The  error is:
PSS analysis does not support behavioral module with hidden states.

I can't quite see why it would fail that way if you've explicitly marked the veriloga block as an instrument_module (although you'd have to make sure that the output was a constant when used in this mode).

A simpler approach might be to just have another view of the cell with the Verilog-A block and just have (say) a schematic view with a dc voltage source with the value set by a variable (set in ADE by the calcVal from the other test) and then use config view to pick that view instead for this test.

Andrew

Are you saying that when using (* instrument_module *) the output has to be constant only in the PSS test? It is actually forced to 0 by a parameter which I change between tests. But the inputs to the block are not constant. Do they also have to be for this to work ?

I didn't quite get your suggestion for the simpler approach. I  wanted to  run the two tests - offset search and pnoise together so they can exchange results though calcVal. But how can I make the config  pick a different view depending on the test I run?

Are you saying that when using (* instrument_module *) the output has to be constant only in the PSS test? It is actually forced to 0 by a parameter which I change between tests. But the inputs to the block are not constant. Do they also have to be for this to work ?

I didn't quite get your suggestion for the simpler approach. I  wanted to  run the two tests - offset search and pnoise together so they can exchange results though calcVal. But how can I make the config  pick a different view depending on the test I run?

The output doesn't have to be constant - it would need to be periodic though if it was time-varying. It just cannot be dependent upon the input signals because if so the behaviour of the block needs to be captured in the solution - and so any variable that is part of that dependency within the model cannot be a hidden state (and just pretending that it's not a hidden state would likely lead to convergence failure or the wrong answer). So the inputs don't need to be constant - it's really all about whether the output is dependent upon the inputs.

If you have two tests in Assembler, there's no need for the config view used to be the same for both tests - so I was suggesting that you have a different config view for the pss/pnoise test which picks a different view for the block that is veriloga in the first test.

Andrew

Hi Andrew,

So if I have two tests in the assembler that are executed in the same run, both of them enabled in the same run, how do I set one of them picking up one config and the other one picking up a different config?

Svilen

Use Right Mouse->Design over the test name and pick the config you wish to use for that test. It's the same as picking a different schematic - each test has its own "design" - if the design is a config, it can be the same top level schematic but configured in different ways for each test by having a different config view for each test.

Andrew

Got it, thanks. Let me try and I will update.

Hi Andrew,

Your approach is doing exactly what I needed. Thanks for the help.

Svilen