$analog_node_alias() usage with vector nets

Hello,

I have a top testbench containing design under simulation (DUT - schematic) and next to it I would like to have a checker built with verilogA. My intent is to use $analog_node_alias() or $analog_port_alias() tasks to bind electrical nets within the checker to the one inside the DUT. Something similar to this: 

module checker;

electrical nd1;
electrical [1:0] nd2;

analog initial begin 

   $analog_node_alias(nd1, "$root.DUT.scalar_net_of_interest");  // having only this line seems to work as expected
   $analog_node_alias(nd2, "$root.DUT.vector_of_interest<1:0>"); // when trying to probe electrical vectors the simulation would run, but nd2 would be always read 0V

end 

analog begin 
    V(nd1) <+ I(nd1)*1k;
    V(nd2[0]) <+ I(nd2[0])*1k;
    V(nd2[1]) <+ I(nd2[1])*1k;
end

endmodule

When I run the simulation ( using Spectre Version 20.1.0.269.isr8 64bit -- 30 Jun 2021) there are no errors in the logfile, but the aliased nets nd1 and nd2 are behaving strange. When I remove the vector nd2 alias function, the nd1 would be the value I expect, but when I try to include it, both nd1 and nd2 become 0V and still no error/warning is reported. 

So I mainly have two questions:

1. What is the right way to access vectors using $analog_node/port_alias() tasks? Should there be special character escapes, like "vect_of_interest\<1:0\>" or anything specific to the vector access syntax?
2. Are there any other ways of binding to nets across the design hierarchy? 

Best regards,

Dimitar