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Polysilicon in 180nm TSMC

LuigiFassio

Hi all, 

I'm going crazy in understanding what is poly layer in 180nm TSMC. 

From my knowlodge i know is n+ polysilicon. From the DRC error looks like is p+ because the error call the poly as P GATE. 

In all the thecnology document i cannot find something that explain all the layer that i can use in the layout. I found one that explain just the common layer. 

if I just place a poly square on the psub there will be also the oxide? 

thanks a lot for the help Slight smile

Parents

  • I believe that P GATE stands for poly-gate, rather than specifying that it's n or p doped poly. I don't think TSMC releases the details of the materials they use in the devices. As a designer you get their pcells and spectre models to work with.

    I don't know whether the oxide will automatically be added below poly rectangle without a FET indicator underneath, but some kind of insulating material between substrate and poly is assumed. But unless the poly metal is used correctly, it won't pass the Design Rule Check and thus won't be fabricated.

    Do you mind specifying the goal of your exercise? Are you trying to build a custom device? If it passes DRC and is able to be fabricated, how can you predict it's performance without a model?

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  • I believe that P GATE stands for poly-gate, rather than specifying that it's n or p doped poly. I don't think TSMC releases the details of the materials they use in the devices. As a designer you get their pcells and spectre models to work with.

    I don't know whether the oxide will automatically be added below poly rectangle without a FET indicator underneath, but some kind of insulating material between substrate and poly is assumed. But unless the poly metal is used correctly, it won't pass the Design Rule Check and thus won't be fabricated.

    Do you mind specifying the goal of your exercise? Are you trying to build a custom device? If it passes DRC and is able to be fabricated, how can you predict it's performance without a model?

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