Simulating standard cells to calculate energy on a cell level

Hi Karthik,

The LEF file would typically only contain abstract data so not enough. "Composer" might be the schematics which you could use, although you're not going to get parasitic effects in those cases. You probably need the real layout (GDS or OA) for that.

I suggest you contact customer support as this probably needs a more detailed discussion on what you're trying to do.

Regards,

Andrew

Thank you for your reply Andrew.

Andrew Beckett said:

"Composer" might be the schematics which you could use, although you're not going to get parasitic effects in those cases.

That's okay, I am only interested in the transistor sizes. Would you please point me to some documentation that describes how to use "Composer" schematics?

Thanks,

Karthik.

Composer is the old product name for the Virtuoso Schematic Editor, so presumably you don't need to know how to use that? There's a possibility that the database might be for CDB (the IC5141 database) and so maybe it needs migrating to IC61X first - using the cdb2oa translator (note this has been removed in later IC618 versions since it's 10 years since the last hotfix of IC5141), but I've no idea what data you've actually got so that may not be relevant!

Andrew

> Composer is the old product name for the Virtuoso Schematic Editor

Oh! I wasn't aware.

I used the cdb2oa converter in the conversion toolbox accessible from the CIW, but my symbols don't seem right. The pins are not usable (they don't connect) in a schematic. Perhaps I'm doing something wrong.

To give you a brief idea about what I'm doing, I want to access the outputs to standard cells provided by some IP vendor (this is a design package, i have a tapeout kit for another technology node, but not the transistor models/PDK). I want to compare standard cells that I design (at this level, it's a schematicSymbol).

To be able to perform such a comparison, I need to access the current and voltage waveforms in ViVA for both my standard cells (which I can), and the ones from the IP vendor. 

My question is, how do I access voltage, current, power waveforms in ViVA for standard cells provided by IP vendors?

Given that I do not have the layout or netlist information for this library as it is a design package and not a tapeout kit.

This following line may be a little irrelevant, but is it possible to simulate standard cells in the same way described above (and see the output in ViVA) if I don't have the spice and spectre models (for the transistors), but I have full netlist and layout information (GDS, this one is a tapeout kit)? Is there a way to go back from the GDS, and simulate the standard cells to see output in ViVA?

Thank you so much for your patience.

Regards,

Karthik

As I said, contacting customer support is really the only option here since I can't see what you've done or what you've got available. 

If you don't have the transistor models, simulating it is going to be rather a challenge! There's almost certainly no data about voltage, current or power waveforms in the data you've got - there's almost certainly some information in the liberty files (.lib) but that's not really in the form of voltage, current or power "waveforms".

Perhaps you should just speak to the IP vendor?

Andrew

I am not sure this will help.

If the vendor's . lib file has CCS/ccsp or ecsm/ecsmp data, you may be able to plot the current/voltage waveform, or convert the current to voltage waveform. You will have to know how the CCS/ecsm . lib was modelled. 

I don't know what you want to achieve. If you want to compare the timing/power of two . lib files, it can be easily done with liberate/compare_library command. 

Guangjun

Guangjun Cao said:

I don't know what you want to achieve.

I want to compare energy efficiency. 

Andrew Beckett said:

Perhaps you should just speak to the IP vendor?

Okay, I will write to imec.

Thank you for your patience!

Regards,
Karthik