Stats

  • Locked Locked
  • Replies 3
  • Subscribers 125
  • Views 16918
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Voltage controlled Current source (VCCS) for ideal OTA

Charanraj Mohan

Hello,

I have designed an OTA that has spec details such as- i) Gain (Av) = 43.2 dB, ii) Phase margin (PM) = 85.55 degree, iii) GWB = 430 kHz. The OTAs are used in the pixel circuit as shown in the below figure-

pixel circuit

I want to use ideal OTA using VCCS and compare its results with the results of the non-ideal (one with the transistors) one. I am puzzled with the connection of VCCS and where to feed the manual spec details such as gain ,PM & GWB. In my understanding the current is the source and voltage is the output. Can you describe how the connections are made for replacing he OTAs in the above pic by VCCS ?

 Thanks in advance!

  • Andrew Beckett

    I'm not sure why you would be expecting an ideal voltage-controlled current source to have phase margin and gain bandwidth parameters. Surely it wouldn't be very ideal then? Put simply, the vccs dependent source in Spectre (if that's the simulator you're trying to use - you didn't say) does not have such parameters and I wouldn't expect them to.

    I'm a bit confused by your circuit above too - if those OTAs have current outputs, it's not clear where the currents are flowing. Clearly you're using the voltage at the output and it's not obvious to me what these OTAs are doing (OTA-B and OTA-C look more like voltage output comparators, since they are open loop).

    Andrew

  • Charanraj Mohan
    in reply to Andrew Beckett

    Thanks Andrew.

    Okay. Am using Spectre simulator. I have used a VCCS. I have attached the screenshot of it. Is it okay ? I have used +/- 20 nA as it is the bias current of the OTA.

    Yes, am using voltage at the output and OTA-B & OTA-C act like comparators. In principle, vdiff resets to vref when it reaches vup or vdown.

  • Andrew Beckett
    in reply to Charanraj Mohan

    No idea whether that's what you want here - it's your circuit. That means the vdiff will swing to +/-200uV which seems quite low, and then I think voutup/down will have a maximum of 0.8uV (which is below the vabstol default tolerance for the simulator and I rather doubt will be high enough for the logic gate that follows it to trigger).

    Probably you need to think about the circuit/modelling a bit more!

    Andrew

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.