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VerilogA loop generate constructs not defining multiple sub modules

AAbdelRahman

Hi,

I am using Cadence ICADVM20.1-64b.200.21 with SPECTRE20.1.231.isr6 64bit

I am using very simplified codes here (empty modules) to simplify the problem statement. Similar behavior is happening with much more complex VerilogA modules. This is why I am asking in the first place. I am mentioning this as a disclaimer for the fact that the codes may seem not to do any useful function.

Here is the problem, 

When using the loop generate construct inside my parent instantiating module (test_parent) to repeatedly instantiate child modules (test1) and (test2), only the first one (test1 in this situation) is recognized, and have the "ahdl_include" statement generated for it in the attached netlist. However, the second one defined (test2 in this situation) is not recognized nor an "ahdl_include" is generated for it in the netlist.

The attached netlist doesn't have a corresponding "ahdl_include" for (test2), and the attached simulation output log is showing a problem recognizing a "defined model" for it. It is ignored for some reason.

I thought I could instantiate several modules the way I am doing. It is done in a similar fashion in the LRM to build an interconnect model comprised of several RC sections. Am I missing something? How can I make sure both modules are instantiated correctly.

Other things I tried:

  1. When both modules are reversed in order of their definition, similar behavior is happening, but now with (test1) instead.
  2. When two for loops are used instead of one, with each one doing instantiation for one of the two modules, similar behavior persists.

 

Ahmed

VerilogA code for test_parent

Fullscreen test_parent_va.txt Download 
// VerilogA for behavioral_blocks, test_parent, veriloga

`include "constants.vams"
`include "disciplines.vams"

module test_parent(in, out);
input in;
output out;

parameter integer N = 9	from [0:inf);

genvar i;

electrical in, out;

generate

	for (i = 0; i < N; i = i+1) begin
		test1 I_TEST1 (in,out);
		test2 I_TEST2 (in,out);
	end

endgenerate

endmodule

VerilogA code for test1

Fullscreen test1_va.txt Download 
// VerilogA for behavioral_blocks, test1, veriloga

`include "constants.vams"
`include "disciplines.vams"

module test1(in, out);
input in;
output out;

electrical in, out;

endmodule

VerilogA code for test2

Fullscreen test2_va.txt Download 
// VerilogA for behavioral_blocks, test2, veriloga

`include "constants.vams"
`include "disciplines.vams"

module test2(in, out);
input in;
output out;

electrical in, out;


endmodule

Generated netlist

Fullscreen 8802.netlist.txt Download 
// Point Netlist Generated on: Dec 28 19:49:26 2021
// Generated for: spectre
// Design Netlist Generated on: Dec 28 19:49:26 2021
// Design library name: behavioral_blocks
// Design cell name: tb_test_parent
// Design view name: schematic
simulator lang=spectre
global 0
include "$SPECTRE_MODEL_PATH/design_wrapper.lib.scs" section=tt_pre
parameters wireopt=11

// Library name: behavioral_blocks
// Cell name: tb_test_parent
// View name: schematic
I0 (net1 net2) test_parent N=9
simulatorOptions options psfversion="1.4.0" reltol=1e-3 vabstol=1e-6 \
    iabstol=1e-12 temp=27 tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 \
    vthmod=vthcc ivthn=300e-9 ivthp=70e-9 ivthw=0 ivthl=0 maxnotes=5 \
    maxwarns=5 digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    checklimitdest=psf vdsatmod=gds 
tran tran stop=10n errpreset=conservative write="spectre.ic" \
    writefinal="spectre.fc" annotate=status maxiters=5 
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
saveOptions options save=allpub
ahdl_include "/home/ahabdelr/workarea/subsampling_MNC_DAC/cadence/behavioral_blocks/test_parent/veriloga/veriloga.va"
ahdl_include "/home/ahabdelr/workarea/subsampling_MNC_DAC/cadence/behavioral_blocks/test1/veriloga/veriloga.va"

Part of the output log of a simple simulation showing the errors

Fullscreen out_log.txt Download 
Error found by spectre in `test_parent_N_9', during hierarchy flattening.
    ERROR (SFE-23): "/home/ahabdelr/workarea/subsampling_MNC_DAC/cadence/behavioral_blocks/test_parent/veriloga/veriloga.va" 20: The instance `I_TEST2_0' is referencing an undefined model or subcircuit, `test2'. Either include the file containing the definition of `test2', or define `test2' before running the simulation.
    ERROR (SFE-23): "/home/ahabdelr/workarea/subsampling_MNC_DAC/cadence/behavioral_blocks/test_parent/veriloga/veriloga.va" 20: The instance `I_TEST2_1' is referencing an undefined model or subcircuit, `test2'. Either include the file containing the definition of `test2', or define `test2' before running the simulation.
    ERROR (SFE-23): "/home/ahabdelr/workarea/subsampling_MNC_DAC/cadence/behavioral_blocks/test_parent/veriloga/veriloga.va" 20: The instance `I_TEST2_2' is referencing an undefined model or subcircuit, `test2'. Either include the file containing the definition of `test2', or define `test2' before running the simulation.
    ERROR (SFE-23): "/home/ahabdelr/workarea/subsampling_MNC_DAC/cadence/behavioral_blocks/test_parent/veriloga/veriloga.va" 20: The instance `I_TEST2_3' is referencing an undefined model or subcircuit, `test2'. Either include the file containing the definition of `test2', or define `test2' before running the simulation.
    ERROR (SFE-23): "/home/ahabdelr/workarea/subsampling_MNC_DAC/cadence/behavioral_blocks/test_parent/veriloga/veriloga.va" 20: The instance `I_TEST2_4' is referencing an undefined model or subcircuit, `test2'. Either include the file containing the definition of `test2', or define `test2' before running the simulation.
    ERROR (SFE-23): "/home/ahabdelr/workarea/subsampling_MNC_DAC/cadence/behavioral_blocks/test_parent/veriloga/veriloga.va" 20: The instance `I_TEST2_5' is referencing an undefined model or subcircuit, `test2'. Either include the file containing the definition of `test2', or define `test2' before running the simulation.
    ERROR (SFE-23): "/home/ahabdelr/workarea/subsampling_MNC_DAC/cadence/behavioral_blocks/test_parent/veriloga/veriloga.va" 20: The instance `I_TEST2_6' is referencing an undefined model or subcircuit, `test2'. Either include the file containing the definition of `test2', or define `test2' before running the simulation.
    ERROR (SFE-23): "/home/ahabdelr/workarea/subsampling_MNC_DAC/cadence/behavioral_blocks/test_parent/veriloga/veriloga.va" 20: The instance `I_TEST2_7' is referencing an undefined model or subcircuit, `test2'. Either include the file containing the definition of `test2', or define `test2' before running the simulation.
    ERROR (SFE-23): "/home/ahabdelr/workarea/subsampling_MNC_DAC/cadence/behavioral_blocks/test_parent/veriloga/veriloga.va" 20: The instance `I_TEST2_8' is referencing an undefined model or subcircuit, `test2'. Either include the file containing the definition of `test2', or define `test2' before running the simulation.

 

  • There are some challenges with generating the information needed for hierarchy referenced within generate blocks because there are a parameterized number of instances, and that can't really be represented in OpenAccess. However, other than the navigator in the editor, the main use of this data is to allow the netlister to traverse the hierarchy so I've always thought it would be useful if the hierarchical references would be generated for the default values of any parameters.

    The issue in this specific case is that the mode of Spectre used to extract the port and hierarchy information from VerilogA for consumption by Virtuoso is stopping at the first instance it finds in any generate block. If (for example) you had instantiated the two instances outside of the generate block and then started the loop one higher, then it works - but the challenge there is that the lower limit of N in your example is 0 - and so that means you need to be able to have no instances when N=0. Even if I try having three separate generate blocks (two with if statements with N>0 and one for loop starting from 1), the VerilogA extraction information still only extracts the first instance it finds.

    Maybe it's OK that N is always >=1, in which case your problem can be solved that way. The alternative is to create a file called "addveriloga.scs" (say) and have an explicit:

    ahdl_include "libName/test2/veriloga/veriloga.va"

    If the library is in your working directory, and you add the addveriloga.scs to your working dir, and have "." in the include path in Setup->Simulation Files, then it should get found OK. A bit of a pain, but a workaround to get you moving.

    You probably should report this to customer support. I did a quick search but couldn't find anything reported quite like this (although it was hard to narrow down the search appropriately so I might have missed it). I do think that it's a good idea for the Spectre "DPL" generator to extract the instances found in generate statements with the default values - although that might be hard because it may only be able to do that during elaboration - but hopefully Spectre can be improved to do a better job of referencing all different components that are conditionally instantiated. If you do contact customer support, please post the case number here because I would like to follow the request to R&D that (hopefully) ensues from this. I'd log it myself but it always is better coming from a user not somebody internal.

    Thanks,

    Andrew

  • in reply to Andrew Beckett

    Hi Andrew,

    Thanks for your response. I really appreciate it.

    I have tried what you suggested, but it didn't work (the addveriloga.scs file wasn't even read and the test2 module wasn't defined). So, I went into "Virtuoso ADE Assembler User Guide" and under the "Specifying Tests and Analyses"  Chapter, and the "Specifying Simulation Files" section, I found the following:

    The simulator resolves a relative path by first looking in the netlist directory (relative to where you run the simulation). If the path starts with the . character, the simulator resolves this by looking in the netlist directory first, then in each of the directories specified in Include Paths in the order you type them. The . character does not mean the current directory.

    So, I assume that I have to place my "addveriloga.scs" file in the same path as the netlist. This is impossible as the netlist is generated in a new place with each new interactive history result created.

    So, instead of using ".", I went on with using a full path to another place. My working directory in this situation where I invoked the virtuoso command. i.e., "/home/......./cadence_working_dir". Still, it didn't work.

    The final thing I did is to add the file itself and not the path it is contained within. To do so, I included it as a definition file i.e., "/home/......./cadence_working_dir/addveriloga.scs". Only then, things worked.

    I don't know If I were using the include path correctly or If I missed something.

    Regarding contacting customer support. I don't have the privilege to create support cases. I have to contact our university's representative. It may take a while because of the holidays season.

    I will keep you posted.

    Best regards,

    Ahmed

  • in reply to AAbdelRahman

    Ahmed,

    My apologies - I didn't re-read through what I'd written earlier and I accidentally omitted one key piece of information - that you have to specify the file "addveriloga.scs" as either a model file (in model libraries) or as a definition file. If it had been in the working directory and "." was in the include path, then you could have specified the file name without the path. You found that it worked by adding it as a definition file with the full path, but the full path wouldn't have been needed if the directory it was contained in was in the include path.

    So this was my mistake - I told you what to put in the file, how to set up the include path, but not that you actually have to tell spectre to include the specific file addveriloga.scs!

    Regards,

    Andrew

  • in reply to Andrew Beckett

    Hi Andrew,

    Thanks again. 

    I tried the two cases both as a definition file and as a model file. Both worked fine even without the "." in the include path.

    I thought I should let you know.

    Best regards,

    Ahmed

  • in reply to AAbdelRahman

    Ahmed,

    I filed a change request, CCR 2590851 to request the parser at least outputs information about both sub-modules.

    Regards,

    Andrew

  • in reply to Andrew Beckett

    Hi Andrew,

    Thank you very much.

    Best regards,

    Ahmed

  • in reply to AAbdelRahman

    Hi Ahmed,

    Just to let you know, R&D have fixed the CCR I filed (2590851) and I've tested it. The fix will be in SPECTRE21.1 ISR5, which is due to be available around the 11th March 2021. It now outputs information about both sub-modules and that means that the ahdl_includes should be correctly generated by the ADE netlister.

    Regards,

    Andrew

  • in reply to Andrew Beckett

    Hi Andrew,

    Glad to know this.

    Thanks for letting me know.

    Best regards,

    Ahmed

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