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Performing AMS simulation in cadence virtuoso, the voltage value printed out exceeds the set power supply voltage value

zuiying

Hello! Recently, I am learning to use AMS simulation in virtuoso. I build a circuit of 8421 counter:

During the simulation, I set the power supply voltage for the digital module to 3.3V:

After the transient simulation is completed, I use "results->print->transient node voltage" to view the node voltage:

The result shows that the voltage of some nodes is 5V, which exceeds the maximum 3.3V set. And it seems that only the nodes of the digital circuit part can display specific values, and the nodes of the analog part of the circuit display question marks (Vdd, net3, and net4 are all nodes of the analog circuit part.)

Why is there a 5V result? And why can only the nodes of the digital circuit part display specific values? I don't know where I made a mistake 

Thank you very much!

  • Andrew Beckett

    You must be using an old version (it's always helpful to post specifying exactly which IC subversion you're using - you can see this in the Help->About window), because in current versions (I think this changed in an IC6.1.7 hotfix; I can't quite remember and as it's the Christmas holidays I'm not going to hunt it down ;-) ) it would show something like 0b1 or 0b0 for a digital net. In older versions it would have gone through the default conversion of digital signals to analog which is hardcoded to be 0V for low and 5V for high. There are still a few places where this happens - for example, calling functions like ymax() on a digital waveform will implicitly convert to analog using 0 to 5V. Unfortunately there's no control over this - it's historical and I've not seen any plan to change it. Usually you would workaround it with explicit calculator functions to convert from digital to analog, and then you have the thresholds yourself.

    The values with question mark are probably just because that node was not saved in the simulation results.

    Regards,

    Andrew

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