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VerilogA $fopen issues when used in a loop

AAbdelRahman

Hi,

I am using Cadence ICADVM20.1-64b.200.21 with SPECTRE20.1.231.isr6 64bit.

In my VerilogA module, I am trying to write some values to a file after the simulation ends.

In order not to overwrite the file if it already exists, I first check if the file exists by opening it for reading and checking the returned multi-channel descriptor "fid".

If "fid" returned is not zero, it means a file with a similar name already exists. So, the filename is changed by appending a number at the end, and the trial is repeated in a while loop. Each trial the number is incremented.

At the final step, I create the file by opening it but now for writing.

Each time a file is opened, I make sure it is closed.

The code works fine and creates "file_with_saved_values.I0.vals". The next run when it finds this file, it successfully creates another file "file_with_saved_values_1.I0.vals" and a third one with the third run "file_with_saved_values_2.I0.vals"

For some reason, on trying to do this further, I get an error:

Failed to run the simulation because one Verilog-A $fopen statement has been used to open more than one file. The number of $fopen statements should be more than the number of files to be opened. Specify the correct number of $fopen statements and rerun the simulation.

I simplified the code and testbench (both attached) and reproduced the same error.

Is there something I am doing wrong when using $fopen? What is special about looping exactly 3 times before giving the error?

Best regards,

Ahmed

code

Fullscreen fopen_issue_va.txt Download 
// VerilogA for behavioral_blocks, fopen_issue, veriloga

`include "constants.vams"
`include "disciplines.vams"


module fopen_issue(in, out);

input in;
output out;

voltage in, out;

parameter integer write_to_file = 1 from [0:1];
parameter string filename_base = "~/Desktop/file_with_saved_values";

integer count;
integer fid;
string filename_mod;

analog begin
	@(initial_step) begin	
		$swrite(filename_mod, "%s.%M.vals", filename_base);
		fid = $fopen(filename_mod, "r");
		if(fid != 0) begin
			count = 1;
			while(fid) begin
				$display("fopen_issue %M: file %s already found, will rename and retry", filename_mod);
				$fclose(fid);
				$swrite(filename_mod, "%s_%d.%M.vals", filename_base, count);
				count = count+1;
				fid = $fopen(filename_mod, "r");
			end	// while end
		end	// if(fid) end
		$fclose(fid);
	end	// @(initial_step) end
	@(final_step) begin
		fid = $fopen(filename_mod, "w");
		$display("fopen_issue %M: Final values will be written to file \"%s\".", filename_mod);
		$fclose(fid);
	end	// @(final_step) end
end	// analog end

endmodule

netlist

Fullscreen fopen_issue_netlist.txt Download 
// Point Netlist Generated on: Jan  3 19:15:56 2022
// Generated for: spectre
// Design Netlist Generated on: Jan  3 19:07:18 2022
// Design library name: behavioral_blocks
// Design cell name: tb_fopen_issue
// Design view name: schematic
simulator lang=spectre
global 0
include "$SPECTRE_MODEL_PATH/design_wrapper.lib.scs" section=tt_pre
parameters wireopt=11

// Library name: behavioral_blocks
// Cell name: tb_fopen_issue
// View name: schematic
I0 (net1 net2) fopen_issue write_to_file=1 \
        filename_base="~/Desktop/file_with_saved_values"
simulatorOptions options psfversion="1.4.0" reltol=1e-3 vabstol=1e-6 \
    iabstol=1e-12 temp=27 tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 \
    vthmod=vthcc ivthn=300e-9 ivthp=70e-9 ivthw=0 ivthl=0 maxnotes=5 \
    maxwarns=5 digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    checklimitdest=psf vdsatmod=gds 
tran tran stop=10n errpreset=conservative write="spectre.ic" \
    writefinal="spectre.fc" annotate=status maxiters=5 
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
saveOptions options save=allpub
ahdl_include "/home/ahabdelr/workarea/subsampling_MNC_DAC/cadence/behavioral_blocks/fopen_issue/veriloga/veriloga.va"

  • Dear AadelRahman,

    AAbdelRahman said:

    For some reason, on trying to do this further, I get an error:

    Failed to run the simulation because one Verilog-A $fopen statement has been used to open more than one file. The number of $fopen statements should be more than the number of files to be opened. Specify the correct number of $fopen statements and rerun the simulation.

    I simplified the code and testbench (both attached) and reproduced the same error.

    Is there something I am doing wrong when using $fopen?

    I am not sure if this Cadence On-line support article addresses your error, but thought I would pass it along. It pertains to your error message.

    support.cadence.com/.../ArticleAttachmentPortal

    As far as the code is concerned, my approach to debugging it is to follow your file open statement with a print statement containing the file it is opening and your file closing statement with a second print statement with the filename it is closing. By viewing the log file, it should be pretty clear if you are not closing each file stream you opened.

    I hope these provide some insight....

    Shawn

  • in reply to ShawnLogan

    This isn't related to the article that Shawn references as that's to do with too many files being opened.

    It seems that Spectre is objecting to the very same $fopen statement in the code being used to open more than one file, despite the fact that the previous opened file was closed. I filed a bug CCR for this, 2591482. I can't see a workaround at the moment other than using something like "%D_%T" or "%P" in the filename to make it unique (search in the Spectre User Guide for "Predefined Percent Codes") rather than using this incrementing approach.

    Regards,

    Andrew

  • in reply to ShawnLogan

    Hi Shawn,

    Thanks for spending some time and trying to help.

    Best regards,

    Ahmed

  • in reply to Andrew Beckett

    Hi Andrew,

    Thanks for your help and suggestion.

    I'll give it a try later after figuring out how to adapt my code to it.

    Best regards,

    Ahmed

  • in reply to AAbdelRahman

    Hi Ahmed,

    R&D have fixed the bug in CCR 2591482, and the fix will be available in SPECTRE20.1 ISR15 due to be available on or around 18th March 2022. I've tested the fix and it now works well.

    Regards,

    Andrew.

  • in reply to Andrew Beckett

    Hi Andrew,

    Thanks for letting me know.

    Best regards,

    Ahmed

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