Bonding Wire in Cadence Virtuoso

Where did you read that? As far as I know the only tool in Virtuoso for creating wirebonds is part of the Virtuoso RF Solution (and it's on the Module menu). This flow is using data that comes from the Allegro package and SIP tools, not a package that was imported via stream - in general Virtuoso is not a packaging tool, although the Virtuoso RF flow allows you to edit the different technology fabrics together in a common environment which is useful for ensuring correct alignment and understanding electromagnetic problems that might occur due to interactions between structures on the die, the bond wire and the package and board fabrics.

From what you say you're not talking about Virtuoso RF, hence my request to find out where you read that...

Andrew

Hello Andrew,

Thank you for your reply,

I was referring to this reference:

https://support.cadence.com/apex/techpubDocViewerPage?xmlName=wcoms.xml&title=W%20Commands%20--%20Commands:%20W%20-%20wire%20bond%20escape&hash=pgfId-1036118&c_version=17.4-2019&path=wcoms/wcoms17.4-2019/wchap.html#pgfId-1036118

As I understand also from you there is a different tool for making the wire bonding and advanced packaging, however, we are using the simple DIL package type as seen from the attached image. For this package, a manual connection is possible for me, but as I have explained in my post, I am not able to create a mental connection with angles that are required between the pin and the pad, this might solve my problem.

This is not a Virtuoso manual. It's part of the APD (Allegro Package Designer) documentation, which is the right tool for the job - package design is not part of the Virtuoso flow (with the exception of Virtuoso RF Solution Option).

Andrew

Thank you Andrew for clearing it to me, may I ask you please about the Virtuoso RF Solution, how we could include this tool our installed Cadence, or do we need a new fresh Cadence installation.

Regards

Please contact your account team. It's part of the iCADVM20.1 release, but you need to set particular environment variables and licenses. Search on the support site in the Rapid Adoption Kits for "Virtuoso RF" for some examples (not sure they cover the wire bond creation though - I can't remember - there is an example database, but it may not have been published on the support site).

Andrew

Please contact your account team. It's part of the iCADVM20.1 release, but you need to set particular environment variables and licenses. Search on the support site in the Rapid Adoption Kits for "Virtuoso RF" for some examples (not sure they cover the wire bond creation though - I can't remember - there is an example database, but it may not have been published on the support site).

Andrew

Thank you, Andrew, that was wonderful, I found plenty of information for the Virtuoso RF from the support center and I will go to read it.

Meanwhile, I have found a way of how to create a connection with any angle, I should not use create wire, with create > shape > path and then F3 and changing the anle option to any option and it worked with me.

I hope the following will be my last question :)

As I am imported the packages as .gds stream by the package house provider, they said it is mandatory to fill the chip details in the table given with the package as you can kindly see from the attached image, but I didn't find a tool in layout environment to add text (except when I make label), or there is a way of adding text, and to which layer should be assigned?

Thank you in advance

Senan said:

As I am imported the packages as .gds stream by the package house provider, they said it is mandatory to fill the chip details in the table given with the package as you can kindly see from the attached image, but I didn't find a tool in layout environment to add text (except when I make label), or there is a way of adding text, and to which layer should be assigned?

Er, isn't that just Create->Label? I'm not sure why you think that "text" is something different from creating a label?

I've no idea what layer they are expecting this on - perhaps the same layer that is already there for the existing labels? I don't know how I can answer that question - I can't read the mind of the package house provider.

Andrew

Dear Andrew,

You solved my issue, I thought the label is different from TEXT as it is the case in the schematic design, but now you answered me for this.

Best Regards

Text in schematics are also labels. Some are labels on a particular layer attached to wires for naming nets, and some are just unattached labels on the "text" layer for note information - but they are all labels...

Anyway, glad your issue is solved.

Andrew

thank Andrew you again for your further clarification

Best Regards