Can Verilog-A macro names be swept in Corners Setup of ADE Assembler for Spectre simulations?

I'm currently maintaining multiple verilog-A views for one cell. I specify those views in Corner Setup of ADE Assembler. I'd like to consolidate them into one verilog-A view using `ifdef macro_name and setting the macro_name in Corner Setup of ADE Assembler. I tried adding -va,define VAR("macro_name") in the command line options in Setup->Environment in the test editor, thinking I would be able to set the macro_name variable in Corner Setup of ADE Assmbler. But simulations failed to start if I use VAR() in the -va,define in the command line options. Is there a way to set macro_name in Corner Setup of AFE Assembler? I'm running simulations using Spectre.

I don't think this is possible. I tried various convoluted ways of doing this, but I can't get it to work any way (I even tried having an expression which was a SKILL expression to set a UNIX env var, and then reference that UNIX env var in the userCmdLineOptions - but this doesn't work either).

So I think you'll need an enhancement request. Please contact customer support.

By the way, I combined this with your identical question from January (I know it wasn't answered then, but it needed some investigation and I didn't have the time to look into it then).

Andrew

I don't think this is possible. I tried various convoluted ways of doing this, but I can't get it to work any way (I even tried having an expression which was a SKILL expression to set a UNIX env var, and then reference that UNIX env var in the userCmdLineOptions - but this doesn't work either).

So I think you'll need an enhancement request. Please contact customer support.

By the way, I combined this with your identical question from January (I know it wasn't answered then, but it needed some investigation and I didn't have the time to look into it then).

Andrew