Stats

  • Locked Locked
  • Replies 3
  • Subscribers 125
  • Views 14292
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Checking for LUP and HVESD on cell-level DRC run

Jin W Kwak

Hi Cadence,

From my previous tape-out run, my DRC runs on sub-circuit cells did not check for LUP (Latch-up) and HVESD (High-voltage ESD) errors until I ran DRC on chip-level design. 

Then I was faced with hundreds of LUP and HVESD errors near to the submission deadline. (Please refer to the screenshot below):

So I went back to each sub-circuit block and re-ran DRC, but LUP and HVESD errors still wouldn't appear on sub-circuit level DRC runs. They only appear on the full chip-level DRC run.

Is there any way for me to check for LUP and HVESD errors on sub-circuit level DRC runs, instead of chip-level, so I can find out the errors earlier and fix them during my sub-circuit designs?

This DRC result is from TSMC 0.18um HV BCD process, and I'm wondering if there's anyone out there who's experiencing the same issue or knows how to fix this.

Thank you for your attention,

Jin

Parents
  • Andrew Beckett

    Hi Jin,

    Given that these checks are specific to the technology you're using, you might want to let everyone know which technology/PDK you're using. That way you might find somebody on the forum who is familiar with the technology you're using and can provide advice based on their knowledge. This is not a generic question but a specific technology question.

    Regards,

    Andrew

  • Jin W Kwak
    in reply to Andrew Beckett

    Thank you Andrew. 

    I didn't realize that this could be technology-specific question. I edited my post accordingly.

    I'm wondering if DRC runs from other technologies usually report LUPs and ESD errors at sub-circuit level DRC runs? (I only worked on this one technology I'm currently using, so I don't know how DRC reports in other technologies.)

    Do you happen to know if it's different in other PDKs?

    Jin

  • Andrew Beckett
    in reply to Jin W Kwak
    Jin W Kwak said:
    Do you happen to know if it's different in other PDKs?

    No idea. I have not done any kind of analysis of different rule types and behaviours in different PDKs.

    Andrew

Reply
  • Andrew Beckett
    in reply to Jin W Kwak
    Jin W Kwak said:
    Do you happen to know if it's different in other PDKs?

    No idea. I have not done any kind of analysis of different rule types and behaviours in different PDKs.

    Andrew

Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.