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Problem with systemVerilog netlister in IC618 which stops with cryptical message on a digital schematics in Virtuoso

Emulator

Hello,

Did you face this error when running SV netlister in logical mode (no-PG) netlist on a hierarchical schematics with explicit PG-pins in top-, and intermediate hierarchies ? 

Error _hnlCheckIfBusHasAnyNonSupplySigType: argument #1 should be a database object (type template = "d") - nil
ERROR (OSSHNL-411): Stopping netlisting due to SKILL error while formatting devices. To bypass this
check, set the environment variable oss.core stopNetlistingOnFormatterError

I miss a detailed message on the root-cause, and it looks like an internal call in the SKILL-env.

The reference schematic uses power/ground/signal properties in the schematics for nets and ports. Toplevel and intermediate hierarchies have explicit PG pins.

I am not sure if switching off the Formatter is a good idea. So, any comments ?

Thanks in advance

Kind regards

Greg

  • Hi Greg,

    I found one report of this error, which suggested that it was fixed in ICADVM18.1/IC6.1.8 ISR10 (so with .500.10 at the end). If you're using an earlier version, perhaps you can try that or later? If you're already using a later version, please contact customer support as it will need investigating.

    Andrew 

  • in reply to Andrew Beckett

    Hi Andrew, 

    Thanks a lot.

    I've involved our experts. btw I apply IC6.1.8.-64b.500.13 version.

    By mean-time, our expert pointed me to the new SystemVerilog netlister (DNL), instead of applying of the older method located in the Tools-NC-Verilog, which is SI-based and is used by scripts in my environment (the older method here is basically the same as in the schematic - plugIns - Simulation - SystemVerilog).

    So you are right, for the case here one needs the toolversion, and the new DNL SystemVerilog netlister function, too.

    Btw. the corresponding construct in source Verilog-netlist was of type: "\my_bus[0]  [1]", and the root-cause was this imported digital netlist into schematic which contained the mentioned mapping and bus array coding. But, in interest of portability, I removed now the limiting array construct from the origin verilog source.

    Kind regards,

    Greg

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