Stats

  • Locked Locked
  • Replies 2
  • Subscribers 125
  • Views 10849
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Problem with systemVerilog netlister in IC618 which stops with cryptical message on a digital schematics in Virtuoso

Emulator

Hello,

Did you face this error when running SV netlister in logical mode (no-PG) netlist on a hierarchical schematics with explicit PG-pins in top-, and intermediate hierarchies ? 

Error _hnlCheckIfBusHasAnyNonSupplySigType: argument #1 should be a database object (type template = "d") - nil
ERROR (OSSHNL-411): Stopping netlisting due to SKILL error while formatting devices. To bypass this
check, set the environment variable oss.core stopNetlistingOnFormatterError

I miss a detailed message on the root-cause, and it looks like an internal call in the SKILL-env.

The reference schematic uses power/ground/signal properties in the schematics for nets and ports. Toplevel and intermediate hierarchies have explicit PG pins.

I am not sure if switching off the Formatter is a good idea. So, any comments ?

Thanks in advance

Kind regards

Greg

  • Andrew Beckett

    Hi Greg,

    I found one report of this error, which suggested that it was fixed in ICADVM18.1/IC6.1.8 ISR10 (so with .500.10 at the end). If you're using an earlier version, perhaps you can try that or later? If you're already using a later version, please contact customer support as it will need investigating.

    Andrew 

  • Emulator
    in reply to Andrew Beckett

    Hi Andrew, 

    Thanks a lot.

    I've involved our experts. btw I apply IC6.1.8.-64b.500.13 version.

    By mean-time, our expert pointed me to the new SystemVerilog netlister (DNL), instead of applying of the older method located in the Tools-NC-Verilog, which is SI-based and is used by scripts in my environment (the older method here is basically the same as in the schematic - plugIns - Simulation - SystemVerilog).

    So you are right, for the case here one needs the toolversion, and the new DNL SystemVerilog netlister function, too.

    Btw. the corresponding construct in source Verilog-netlist was of type: "\my_bus[0]  [1]", and the root-cause was this imported digital netlist into schematic which contained the mentioned mapping and bus array coding. But, in interest of portability, I removed now the limiting array construct from the origin verilog source.

    Kind regards,

    Greg

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.