VXL and inherited connections?z

I have a schematic, predominantly analog with vss as negative supply. I have a single logic gate instantiated from a ddk with vss! as it's inherited supply.  In simulation, I use netset a couple layers up the hierarchy to set vss! to vss

However, in the layout, of course VXL sees vss! and vss as different nets.  I tried using netset in the actual schematic hierarchy level I'm laying out - remember the netset vss is several layers up in the schematic hierarchy - and set vss! to vss.

However, nothing changes in the layout after an update components and nets.  Still VXL sees vss! and vss as two different nets.

How does one handle this situation?