Cadence tool to analyse across-chip variations (distance-dependent mismatch)?

Dear Stephan,

StephanWeber said:

I wonder, is Cadence offering something here out out the box? E.g. for post-layout simulations? Or in modgens?

As you correctly stated in the beginning of your post, this type of statistical model information is from the foundry as it is technology specific. Cadence does allow, for example, varying the sigma of the Monte-carlo based standard deviation, but without intimate knowledge of the technology, I do not think Cadence can provide this information with any degree of accuracy. Further, this type of information is dynamic in that process changes are made in the foundry regularly that may impact the statistical information. Hence, I cannot imagine that Cadence can track akk the process changes (nor would the foundry likely release the information!) for all the technology files it supports.

StephanWeber said:

The issue is that e.g. the mismatch increases quite rapidly with distance, so the matching of 2 transistors 10um apart is significantly worse than for a layout with no spacing.

You can mathematically capture this in a covariance matrix with entries cab=cba, cbc=ccb and cac=cca, so in the simulation netlist such a matrix needs to be attached to the instances A,B,C for MC random number generation. 

I can tell you that in our case, we have specific model files for use in statistical corners that attempt to capture the impact of what we call "local" and "global" mismatch variation. We are very concerned with the impact of mismatch as it has a first order impact on our device yields. As such, the manner in which we validate its impact is to assure design robustness under N sigma conditions where N is a design dependent variable. In some cases, our designs must be validated with N  as low as 3 and in other designs the design criteria requires robust operation with N >> 3.

My two cents (if it is even worth that!!)....

Shawn

Dear Stephan,

StephanWeber said:

I wonder, is Cadence offering something here out out the box? E.g. for post-layout simulations? Or in modgens?

As you correctly stated in the beginning of your post, this type of statistical model information is from the foundry as it is technology specific. Cadence does allow, for example, varying the sigma of the Monte-carlo based standard deviation, but without intimate knowledge of the technology, I do not think Cadence can provide this information with any degree of accuracy. Further, this type of information is dynamic in that process changes are made in the foundry regularly that may impact the statistical information. Hence, I cannot imagine that Cadence can track akk the process changes (nor would the foundry likely release the information!) for all the technology files it supports.

StephanWeber said:

The issue is that e.g. the mismatch increases quite rapidly with distance, so the matching of 2 transistors 10um apart is significantly worse than for a layout with no spacing.

You can mathematically capture this in a covariance matrix with entries cab=cba, cbc=ccb and cac=cca, so in the simulation netlist such a matrix needs to be attached to the instances A,B,C for MC random number generation. 

I can tell you that in our case, we have specific model files for use in statistical corners that attempt to capture the impact of what we call "local" and "global" mismatch variation. We are very concerned with the impact of mismatch as it has a first order impact on our device yields. As such, the manner in which we validate its impact is to assure design robustness under N sigma conditions where N is a design dependent variable. In some cases, our designs must be validated with N  as low as 3 and in other designs the design criteria requires robust operation with N >> 3.

My two cents (if it is even worth that!!)....

Shawn

Thanks Shawn! Globafoundries is working on this topic since some time in 22FDX technology. They made a big test chip with an array of transistors in a matrix. This way you can check how different e.g. the matching is between two neighbors vs 2 instances with a certain distance. Such ACV plots are also available for older technologies, but now in 28nm and below it starts to matter much more. The difficult part is coming now: Create an improved statistical model for such matrix and implement it to PDK.

At the moment, designers use a model which is wrong for sure. And this is only ok if you follow strict rules, like matched transistor should be close together. However, to achieve matching down to 0.1mV you need larger structures, so within such large structure assuming good matching is far too optimistic.

At ST we put x, y and orientation to the post-layout netlist, but I believe the correlation part is missing so far for general transistor-level simulation. 

Bye Stephan