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Inherited connections and VXL.....again.

kenc184

I thought I understood inherited connections, and i have no issues wrt simulation. But I am not sure of the procedure for having everything correct going from schematic to VXL.

I have put together a trivial example, it is a single inverter which has inh conn for vdd!, vss! and both substrates. In my situation, each substrate is connected to source as is usual.

What I EXPECT when I draw the schematic, is that cellview to cellview to create a symbol gives me a symbol block with IO but without supplies, this works as long as one remembers to check

the "exclude inherited connection pins" from the conversion popup.

I need supply pins in my VXL layout, so that connectivity to supplies can be checked by VXL (unless this is not so with inh conn?) so I use explicit pins in the schematic and assign them to my supplies which are "vplus" and "vss" (no bang)

I assign the substrates implicitly, and a subwelltie cell is needed on the layout to connect to the substrates.

This APPEARS to work, except that the supplies in the layout cells are labelled vss!/vss! and vdd!/vdd! even thought the vplus and vss pins attached to them cause no warning markers.

If I netset all four connections in the inverter to my supplies (second pair of drawings) I get warning markers around my vplus and vss pins even though the cells have vplus and vss defined for their supplies.

What is the correct ay to go from schematic to layout XL?

If I eliminate the explicit pins and use netset on all four connections, then a vdd! and vss! pin are created in the layout. 

Parents
  • Frank Wiedmann

    At https://support.cadence.com/apex/articleattachmentportal?id=a1O0V000006All6UAC there is a Rapid Adoption Kit on Inherited Connections that includes layout and LVS.

  • kenc184
    in reply to Frank Wiedmann

    Thanks Frank, I'll go through he RAK.

  • Andrew Beckett
    in reply to kenc184

    I was going to try this out (lack of time, unfortunately), but in general you would want to use explicit pins with inherited connections on them, as the idea is that the names of the pins in schematic would then define the names of the pins on the layout. The nets themselves though will have the inherited connections and so will probably show using the default values for the net name - so have you tried selecting the pins and using edit properties to see what the actual pin name is?

    Andrew

  • kenc184
    in reply to Andrew Beckett

    I went through the RAK, and it relies on the power pins being defined as globals - in that way they do not propagate to the symbol view, and in the layout appear to match the inherited connection name due to the netset on the schematic.  Like you, lack of time excludes me from trying to get this to work with non -global pin names so I shall simply change my vplus to vplus!, vss to vss!  and move on.

    I would add a picture but that option doesn't seem available to replies to the original post.

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  • kenc184
    in reply to Andrew Beckett

    I went through the RAK, and it relies on the power pins being defined as globals - in that way they do not propagate to the symbol view, and in the layout appear to match the inherited connection name due to the netset on the schematic.  Like you, lack of time excludes me from trying to get this to work with non -global pin names so I shall simply change my vplus to vplus!, vss to vss!  and move on.

    I would add a picture but that option doesn't seem available to replies to the original post.

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