Importing Digital Standard Cells from PDK data

Hello everybody,

I have some problems including the digital library with the standard cells in it in Virtuoso (same accounts for the standard IO-library).

I have included the cds.lib files from this PDK which was fine. Problem: Contrary to the other processes I know, there is only a symbol in it (no schematics and layout).

What I would like to have are symbol+schematic+layout (ideally).

What I have understood so far is that I can include the schematics from the cdl-file with all the subcircuits.

I used Spice-In with the options:

- Netlist language CDL refering to the netlist file

- Import Sub-circuits List: empty (I want to include all)

- Reference Library list: I referenced the library created with all the symbols (called it PDK_digital), and the library which contains the transistor models (PDK).

- I have no device mapping file (I guess here is the problem, but the mapping should be straight-forward, since I have one symbol which has the same name as the subcircuit-entry in the cdl file).

- Output library is the library with the digital symbols (PDK_digital). I also tried it with a new library

Problem: Nothing happens

Log file:===================
Spice In Log File
===================
Parameter file: /tmp/spiceInPn57939
Import Parameters:
    Netlist file name: /nas/ei/share/pdks/GF/GF22FDX_SC8T_104CPP_BASE_CSC20SL_FDK_RELV06R50/cdl/GF22FDX_SC8T_104CPP_BASE_CSC20SL.cdl
    Output library name: cmos22fdsoi_digital
    Output View Type: schematic
    Schematic view name: schematic
    Netlist view name: netlist_tmp
    Reference Library List: cmos22fdsoi cmos22fdsoi_digital cmos22fdsoi_digital
    Device-mapping not enabled.
    Master Cell for Ground: gnd
    Cells to be Overwritten: <all>
    Schematic Generation parameter file: /tmp/schOpts_spiceInPn57939
    Simulator: spectre
    Output Simulator: spectre
    paramCaseValue: default
    Parser: ASSURA
    Language: CDL
WARNING (SPICEIN-99): 'Import Subcircuit List' is not found in the specification, hence setting it to
default empty value and importing all sub-circuits in the netlist.
INFO (SPICEIN-100): SpiceIn successfully parsed the cdl netlist file '/nas/ei/share/pdks/GF/GF22FDX_SC8T_104CPP_BASE_CSC20SL_FDK_RELV06R50/cdl/GF22FDX_SC8T_104CPP_BASE_CSC20SL.cdl'.

Importing SUBKCT 'tdndsx' in Library 'cmos22fdsoi_digital'
    Master Cellview Found in cmos22fdsoi::tdndsx::symbol
    Skipping import for subckt: tdndsx

Basically all cells are skipped.

For the layout I am completely blank, there is a huge gds file in the pdk directory.

Is there a straight forward way to include the files? I would be very thankful if anybody can help with this process.

Kind regards,

Matthias