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LVS Port Mismatch Errors with CDL Netlist

amrao

Hello,

I have a schematic and layout that I'm trying to run through LVS using PVS 16.15.

The schematic contains a number of sub-blocks which come from an IP provider and

only have a CDL netlist available. I include these CDL netlists in the LVS run but I get many mismatch errors

on the sub-blocks. 

In the LVS form I choose 'Create CDL' which creates the netlist used for LVS. The problem I see is that

the sub-circuit instantiations in the CDL netlist it creates do not have the same port order as the sub-circuit definitions

in the included CDL netlists.

So my question is what determines the port order for the sub circuits in the CDL netlist that is created for LVDS and how

can I ensure that they match the sub circuit definitions in the cdl netlists provided by the IP provider?

I am using IC6.1.8-64b.500.18

Best Regards,

Anand

Parents
  • amrao

    An update on this is that if I edit the auCdl view for one of the sub blocks I see that the pin order is different from

    the cdl netlist that I include, so this seems to be the source of the error. The funny thing is that the pin order is different

    when I open this cell view in another environment and is actually the same as the included netlist. Is there some environment

    variable that determines the order of the auCdl view?

Reply
  • amrao

    An update on this is that if I edit the auCdl view for one of the sub blocks I see that the pin order is different from

    the cdl netlist that I include, so this seems to be the source of the error. The funny thing is that the pin order is different

    when I open this cell view in another environment and is actually the same as the included netlist. Is there some environment

    variable that determines the order of the auCdl view?

Children
  • amrao
    in reply to amrao

    The problem appears to be that when we updated our tool version the port order for the auCDL netlister has changed.

    The solution that works is to add the line auCdlCDFPinCntrl='t to the .simrc file where virtuoso is started. This corrects 

    the port order mismatch between the CDL netlist and the cdl netlists from the IP provider. Now the LVS passes.

  • Andrew Beckett
    in reply to amrao

    This hasn't changed in different versions. If you have an external block you normally need to have the termOrder defined in the auCdl simInfo in the CDF for the block. The auCdlCDFPinCntrl is normally only needed to control the top-level pin order and the intermediate pin order (by default it would use some sorted order - I think sorted outputs, inouts and then inputs - but I can't remember; normally it doesn't matter because it's self-consistent). The leaf level always needs control over the terminal order (for devices, for example).

    Anyway, glad you got it working.

    Andrew

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