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Monte Carlo: How to use different configs during calibration and simulation while keeping corner and mismatch information

ExcaIibur

During calibration, usually only a part of the circuit needs to be simulated while the remaining 80% of the netlist has no impact on the simulation of the sub-circuit being calibrated. 

And during simulation, the sub-circuit that was calibrated is not needed. For example, if the sub-circuit provides a sine wave and the whole purpose of calibration is to calibrate the amplitude of the sinewave so that this sub-circuit can be replaced by amplitude-calibrated sine wave, to reduce simulation time.

However, it seems that doing it in the straight-forward way (swapping the config) cannot maintain the Monte Carlo corner or mismatch, rendering the calibration useless.

I read the documentation "Techniques for Simulating Calibrated Circuits, Virtuoso ADE Assembler, Rapid Adoption Kit, Product Versions:IC6.1.7 ISR15 / ICADV12.3 ISR15". It says:
    "The statistical mismatch parameter values have a dependency on the order of the instances in the netlist"

This seems to suggest that any modification to the netlist, even the order of instances, would break the MC corner and misamtch.

Therefore, I would like to ask whether there is a way to swap the cofnig of a top-level DUT(making partA of the DUT empty for calibration while making partB of the DUT empty for simulation) while maintaining MC corner and mismatch. 

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  • JohnTweed

    I'm not completely sure about this, and so someone may correct me....
    If you run M/C with process corners only, then each component of the same type receives the same variation. (No mismatch).  In this case I don't see that the drawing process of M/C would impact your results, because it's not instance based.
    So then the question becomes about the mismatch variation on top of the process variation.  How correlated is the mismatch of your first block to the second block?

    You can always run a short test with say 5 samples, with the full circuit in place for both tests, then compare to the same test with the reduced circuit framework.

    That will be a sanity check for you.  If it works then move on to the full M/C sweep.

Reply
  • JohnTweed

    I'm not completely sure about this, and so someone may correct me....
    If you run M/C with process corners only, then each component of the same type receives the same variation. (No mismatch).  In this case I don't see that the drawing process of M/C would impact your results, because it's not instance based.
    So then the question becomes about the mismatch variation on top of the process variation.  How correlated is the mismatch of your first block to the second block?

    You can always run a short test with say 5 samples, with the full circuit in place for both tests, then compare to the same test with the reduced circuit framework.

    That will be a sanity check for you.  If it works then move on to the full M/C sweep.

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