Community Custom IC Design connectivity in layout
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connectivity in layout

paulinho

I have run LVS on my layout and its clean (provided I'm giving 'Ignore layout and source ports during comparison'). However when I do  Connectivity->Check against source, I do see 'Incomplete nets' in the 'Connectivity' tab as shown below.

All of them have similar description...Open on net ***, "Unimplemented terminal 'b' of instance ****"

Is this something which needs to be taken care of, even though the LVS appears clean ?

Parents

  • This means that the transistor pcells don't have a bulk pin, and haven't got the information on them to tell layout XL to ignore the missing pin. Sometimes this is done in the PDK, but if not the bulk connection would probably be checked in LVS instead as it's shared via a bulk or well connection.

    Anyway, I don't think it's necessary to do anything to your layout to fix this. You might want to feed back to the PDK provider to ask them to improve this.

    Andrew

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  • This means that the transistor pcells don't have a bulk pin, and haven't got the information on them to tell layout XL to ignore the missing pin. Sometimes this is done in the PDK, but if not the bulk connection would probably be checked in LVS instead as it's shared via a bulk or well connection.

    Anyway, I don't think it's necessary to do anything to your layout to fix this. You might want to feed back to the PDK provider to ask them to improve this.

    Andrew

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