SystemVerilog generate loop does not compile modules defined inside loop

Hello,

I am using Virtuoso IC6.1.8-64b.500.23, Spectre 21.1.0.303.isr5, and Xcelium 21.09-s005 with AMS simulator. 

I have a SystemVerilog code that simply creates multiple sine waves as shown below:

module GET_SIGNALS
#(
parameter ADD_OFFSET = 1,
parameter TIMESCALE_T = 1e-6,
parameter SIGNALS_COUNT = 16
)
(
// Inputs
clk,
rst,
A_bank,
f_bank,
p_bank,
A_offset_bank,
f_offset_bank,
p_offset_bank,
t_delay,

// Outputs
out
);

// ------------------------
// Input ports definitions:
// ------------------------
input clk;
input rst;
input real t_delay;
input real A_bank [SIGNALS_COUNT-1:0];
input real f_bank [SIGNALS_COUNT-1:0];
input real p_bank [SIGNALS_COUNT-1:0];
input real A_offset_bank [SIGNALS_COUNT-1:0];
input real f_offset_bank [SIGNALS_COUNT-1:0];
input real p_offset_bank [SIGNALS_COUNT-1:0];

// -------------------------
// Output ports definitions:
// -------------------------

// Output filtered data
output real out [SIGNALS_COUNT-1:0];

// ------------------------------
// Module Parameters & Variables:
// ------------------------------
real signal [SIGNALS_COUNT-1:0];
real offset [SIGNALS_COUNT-1:0];

// Call sine wave generator module:
// --------------------------------

genvar itr;
generate
for (itr=0; itr<SIGNALS_COUNT; itr=itr+1) begin

SINE #(.TIMESCALE_TB(TIMESCALE_T)) sin (.sampling_clock(clk),
.freq(f_bank[SIGNALS_COUNT-1-itr]),
.offset ($itor(0)),
.ampl(A_bank[SIGNALS_COUNT-1-itr]),
.phase(p_bank[SIGNALS_COUNT-1-itr]),
.t_delay(t_delay), .sine_output(signal[itr])
);

SINE #(.TIMESCALE_TB(TIMESCALE_T)) sin_o (.sampling_clock(clk),
.freq(f_offset_bank[SIGNALS_COUNT-1-itr]),
.offset ($itor(0)),
.ampl(A_offset_bank[SIGNALS_COUNT-1-itr]),
.phase(p_offset_bank[SIGNALS_COUNT-1-itr]),
.t_delay(t_delay),
.sine_output(offset[itr])
);
end
endgenerate

// Combinational Logic:
// --------------------
always @ (*) begin

// Initialize data
if (!rst)
begin
for (integer i=0; i<SIGNALS_COUNT; i=i+1)
begin
out[i] = 0;
end

end
else
begin
for (integer i=0; i<SIGNALS_COUNT; i=i+1)
begin
out[i] = ADD_OFFSET? signal[i] + offset[i] : signal[i];
end
end
end

endmodule

This module calls another module called SINE, defined below:

import "DPI-C" pure function real sin (input real rTheta);

// Module Parameters & Definitions:
// --------------------------------
`define PI 3.14159265

module SINE
#(
parameter TIMESCALE_TB = 1e-6
)
(
// Inputs
sampling_clock,
freq,
offset,
ampl,
phase,
t_delay,
// Outputs
sine_output
);
// ------------------------
// Input ports definitions:
// ------------------------
input sampling_clock;
input real freq;
input real offset;
input real ampl;
input real phase;
input real t_delay;

// -------------------------
// Output ports definitions:
// -------------------------
output real sine_output;

// Required variables:
// Sine wave time:
real time_s;
// Sine wave sampling clock:
reg sampling_clock = 1'b0;

// ------------
// Main Module:
// ------------
// Time scaling factor to convert actual simulator time into real time:
always @(posedge sampling_clock) begin
time_s <= $time*TIMESCALE_TB;
end

assign sine_output = offset + (ampl * sin((2*`PI*freq*(time_s-t_delay))+phase));

endmodule

Both modules are saved and compiled as SystemVerilog veiws in Cadence Virtuoso and symbols are instantiated in a schematic view. On simulating this in a test bench, I notice that the config view doesn't recognize the SINE module!

Hence, I get this error in xrun.log:

SINE #(.TIMESCALE_TB(TIMESCALE_T)) sin (.sampling_clock(clk),
|
xmelab: *F,OSDINF (~/TDMA_uECoG_Project/GET_SIGNALS/systemVerilog/verilog.sv,83|49): instance 'TB_TDMA_uECoG.analog_module@TDMA_ANALOG_MODULE<module>.get_signals_module@GET_SIGNALS<module>.genblk1[0].sin' of design unit 'SINE' is a leaf instance and is unresolved in cellview 'TDMA_uECoG_Project.GET_SIGNALS:systemVerilog'. Ensure that the design unit is either pre-compiled or its corresponding text file is specified for compilation. Also, check the binding for this instance in Cadence Hierarchy Editor to confirm if it is set to externalHDL or addStopPoint or if nlAction is set to 'stop' for the specified instance.

If I unrolled the generate block loop manually (which is very painful!), the simulator runs fine. I tried to instantiate a dummy SINE block outside generate loop to make config view pick it up (which it did), but I got the same error.

Is there something I might be missing or is this a bug?

Kindest Regards,

Nader Fathy