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Digital components library for CMOSP18 in IC6 or IC5 in transistor level

HamedN

Hi,


I am trying to design a digital logic with some AND, OR, NOT, and DFF components. I am wondering if you could help me to figure out whether there are any libraries for CMOSP18 including these gates in transistor level.  

For the new PDK (6.13a), I am trying to use the "sample" library, but when I am trying to use any component of this, the following error is occurring:
---------------------------
 ERROR (SFE-23): "input.scs" 33: The instance `_3' is referencing an undefined model or subcircuit, `nmos'. Either include the file containing the definition of `nmos', or define `nmos' before running the simulation.
---------------------------
Also, for the old PDK (5.18.2),  I am trying to use the "vst_n18_sc_tsm_c4" library, but when I am trying to use any component of this, no output is displayed. It seems that it is just on a behavioral level.
I would appreciate it if anyone could help me to figure out this issue.
Thanks in advance for your time and kind consideration.

Best regards,
Hamed
Parents
  • Andrew Beckett

    Hamed,

    The sample library is not really intended as a digital cell library - it's a very old set of samples, and is not set up for any particular PDK nor even set up to work with ADE.

    You should contact the foundry to see if they have any standard cell libraries available (I don't know which foundry this is).

    Andrew

  • HamedN
    in reply to Andrew Beckett

    Hi Andrew,

    I do appreciate your quick reply and your time.

    So, you mean there is standard cell libraries which are in transistor level design, which I can insert in my analog design and run the spectreS simulator.

    Am I correct?

    Thanks again for your help.

    Hamed

  • Andrew Beckett
    in reply to HamedN
    HamedN said:
    So, you mean there is standard cell libraries which are in transistor level design, which I can insert in my analog design and run the spectreS simulator.

    Well, I rather doubt you want to be using spectreS, because that is the old socket interface to spectre which has been obsolete for more than 20 years. However, you ought to be able to get a transistor level description from either a foundry or a standard cell library provider (such as ARM; other providers are available). Then you can simulate these with Spectre and your PDK (I expect - I don't know which technology "CMOSP18" is though).

    Andrew

Reply
  • Andrew Beckett
    in reply to HamedN
    HamedN said:
    So, you mean there is standard cell libraries which are in transistor level design, which I can insert in my analog design and run the spectreS simulator.

    Well, I rather doubt you want to be using spectreS, because that is the old socket interface to spectre which has been obsolete for more than 20 years. However, you ought to be able to get a transistor level description from either a foundry or a standard cell library provider (such as ARM; other providers are available). Then you can simulate these with Spectre and your PDK (I expect - I don't know which technology "CMOSP18" is though).

    Andrew

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  • HamedN
    in reply to Andrew Beckett

    Thanks, I got your point.
    Actually, now I am able to run the simulation. My PDK is cmosp18.5.2, and I found the standard cell library of "vst_n18_sc_tsm_c4", and now I am able to run it.
    The only difference is there is no view of cells in transistor level, however there is "extracted" view, so do you think it will be fine to use that.

    I really do appreciate your valuable time and consideration.

    Hamed 

  • Andrew Beckett
    in reply to HamedN

    Probably. I have no idea about the origins of these libraries (the PDK name and library aren’t familiar) so I can’t guarantee anything about what it is you’re simulating.

  • HamedN
    in reply to Andrew Beckett

    I see, by the way, I do appreciate your valuable help.

    Best wishes,

    Hamed

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