Spectre/Verilog-A: how to avoid small time step issues due to @cross() event?

Jorge,

The bigger problem is that the simulation blows up, which is because the output of the MUX is a voltage source which changes instantaneously and then drives an ideal capacitor with no resistance - so there's no time constant - this leads to a huge instantaneous current to try to charge up the capacitor when the voltage changes. I put a 1 ohm resistor in series with the load capacitor and that makes things a lot happier (it mostly gets rid of the lint warnings other than the very first). 

The issue with the lint check is really due to the fact that the time step near the beginning is quite small. This is not because of the time tolerance, but the value tolerance (the final argument). If you make that looser (e.g. 0.1) then the warnings go away altogether. 

Even with the default value tolerance (which is what the model is effectively using), it only took 147 time steps (running with APS) in the transient simulation (when I added the 1ohm resistor in series with the capacitor). So that's nothing to worry about. The remaining lint message is just a potential concern - it would be more of a concern if it kept happening.

Andrew

Thanks so much for the reply, Andrew. Adding the resistor and relaxing expr_tol to 0.1 indeed helps a lot. I however get slightly different results (still some warnings and more time steps), any idea on why could this be?:

[...]
Warning from spectre at time = 504.999 ps during transient analysis `tran'.
    WARNING (AHDLLINT-8007): "/[...]/analog_mux_modified/veriloga/veriloga.va" 50: MUX: The cross/above function in the model has imposed a time step size of (537.429 fs), which is too small and might slow down the simulation. Increase the applicable tolerances and/or expression values of the function to avoid such small step size, and for faster simulation.
Warning from spectre at time = 504.997 ps during transient analysis `tran'.
    WARNING (AHDLLINT-8005): "/[...]/analog_mux_modified/veriloga/veriloga.va" 60: MUX: Detected discontinuity in the analog signal contribution, which might cause convergence difficulties and slow down simulation. Add a transition filter on the expression to improve the convergence.
[...]
Number of accepted tran steps =             196

In fact, I get *a lot* of AHDLLINT-8005 warnings in my real circuits/simulations. Is there something fundamentally wrong with the verilog-A model? I mean, is there any way to avoid discontinuities when an analog output is created as the "multiplexation" of analog inputs? There is no such thing as an "analog transition filter", or is it?

Thanks again for your help,
Jorge.

Updated netlist:
simulator lang=spectre
global 0
CK (vCLK 0) vsource type=pulse val0=0 val1=1 period=1n
IN (vIN 0) vsource dc=500.0m phase=90 type=sine ampl=500.0m freq=497M
MUX (vIN 0 vCLK net4) analog_mux_modified vth=0.5
LOAD (vOUT 0) capacitor c=1p
Rdamping (net4 vOUT) resistor r=1
simulatorOptions options psfversion="1.4.0" reltol=1e-3 vabstol=1e-6 \
    iabstol=1e-12 temp=27 tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 \
    maxnotes=5 maxwarns=5 digits=5 cols=80 pivrel=1e-3 \
    sensfile="../psf/sens.output" checklimitdest=psf
tran tran stop=2n errpreset=conservative write="spectre.ic" \
    writefinal="spectre.fc" annotate=status maxiters=5
save vIN vCLK vOUT
ahdl_include "[...]/analog_mux_modified/veriloga/veriloga.va"

Updated analog_mux Verilog-A model:
[...]
(* instrument_module *)
module analog_mux_modified(vin1, vin2, vsel, vout);
input vin1, vin2, vsel;
output vout;
electrical vin1, vin2, vsel, vout ;
parameter real vth  = 2.5;

   integer selector;
   real vout_val;

   analog begin
      selector = (V(vsel) > vth) ? 1: 0;

//      @ (cross(V(vsel) - vth, 1, 1.0, vsel.potential.abstol))
      @ (cross(V(vsel) - vth, 1, 1.0, 0.1))
         selector = 1;

//      @ (cross(V(vsel) - vth, -1, 1.0, vsel.potential.abstol))
      @ (cross(V(vsel) - vth, -1, 1.0, 0.1))
         selector = 0;

      if (selector == 1)begin
         vout_val = V(vin1);
      end
      else if (selector == 0)begin
         vout_val = V(vin2);
      end

      V(vout) <+ vout_val;
   end
endmodule

More detailed simulator log excerpt:
Spectre (R) Circuit Simulator
Version 20.1.0.269.isr8 64bit -- 30 Jun 2021
[...]
Command line:
     \
        /[...]/tools/bin/spectre  \
        -64 input.scs +escchars +log ../psf/spectre.out -format psfxl  \
        -raw ../psf ++aps +lqtimeout 0 -maxw 5 -maxn 5 +lsusp -env ade  \
        -ahdllint=warn -ahdllibdir  \
        [...]/maestro/results/maestro/Interactive.8/sharedData/CDS/ahdl/input.ahdlSimDB  \
        +logstatus
[...]
Loading /[...]/tools.lnx86/cmi/lib/64bit/5.0/libinfineon_sh.so ...
Loading /[...]/tools.lnx86/cmi/lib/64bit/5.0/libphilips_o_sh.so ...
Loading /[...]/tools.lnx86/cmi/lib/64bit/5.0/libphilips_sh.so ...
Loading /[...]/tools.lnx86/cmi/lib/64bit/5.0/libsparam_sh.so ...
Loading /[...]/tools.lnx86/cmi/lib/64bit/5.0/libstmodels_sh.so ...
Reading file:  /[...]/maestro/results/maestro/Interactive.8/1/sch/netlist/input.scs
Reading file:  /[...]/tools.lnx86/spectre/etc/configs/spectre.cfg
Reading file:  /[...]/analog_mux_modified/veriloga/veriloga.va
Reading link:  /[...]/tools.lnx86/spectre/etc/ahdl/constants.h
Reading file:  /[...]/tools.lnx86/spectre/etc/ahdl/constants.vams
Reading link:  /[...]/tools.lnx86/spectre/etc/ahdl/discipline.h
Reading file:  /[...]/tools.lnx86/spectre/etc/ahdl/disciplines.vams
[...]
Global user options:
         psfversion = 1.4.0
            vabstol = 1e-06
            iabstol = 1e-12
               temp = 27
               gmin = 1e-12
             rforce = 1
           maxnotes = 5
           maxwarns = 5
             digits = 5
               cols = 80
             pivrel = 0.001
           sensfile = ../psf/sens.output
     checklimitdest = psf
             reltol = 0.001
               tnom = 27
             scalem = 1
              scale = 1

[...]
Important parameter values:
    start = 0 s
    outputstart = 0 s
    stop = 2 ns
    step = 2 ps
    maxstep = 20 ps
    ic = all
    useprevic = no
    skipdc = no
    reltol = 100e-06
    abstol(V) = 1 uV
    abstol(I) = 1 pA
    temp = 27 C
    tnom = 27 C
    tempeffects = all
    errpreset = conservative_sigglobal
    method = gear2only
    lteratio = 10
    relref = sigglobal
    cmin = 0 F
    gmin = 1 pS
    rabsshort = 1 mOhm
[...]
    tran: time = 64.15 ps    (3.21 %), step = 20 ps           (1 %)
    tran: time = 164.1 ps    (8.21 %), step = 20 ps           (1 %)
    tran: time = 264.1 ps    (13.2 %), step = 20 ps           (1 %)
    tran: time = 364.1 ps    (18.2 %), step = 20 ps           (1 %)
    tran: time = 464.1 ps    (23.2 %), step = 20 ps           (1 %)

Warning from spectre at time = 504.999 ps during transient analysis `tran'.
    WARNING (AHDLLINT-8007): "/[...]/analog_mux_modified/veriloga/veriloga.va" 50: MUX: The cross/above function in the model has imposed a time step size of (537.429 fs), which is too small and might slow down the simulation. Increase the applicable tolerances and/or expression values of the function to avoid such small step size, and for faster simulation.
Warning from spectre at time = 504.997 ps during transient analysis `tran'.
    WARNING (AHDLLINT-8005): "/[...]/analog_mux_modified/veriloga/veriloga.va" 60: MUX: Detected discontinuity in the analog signal contribution, which might cause convergence difficulties and slow down simulation. Add a transition filter on the expression to improve the convergence.
[...]

Number of accepted tran steps =             196

Maximum value achieved for any signal of each quantity:
V: V(vCLK) = 1 V
I: I(MUX:vout_flow) = 979.6 mA
If your circuit contains signals of the same quantity that are vastly different in size (such as high voltage circuitry combined with low voltage control circuitry), you should consider specifying global option `bin_relref=yes'.
[...]
************ AHDL Lint Summary ************
Number of accepted steps = 196
#Steps Type         Instance:File:Line No.
     1 cross/above  MUX:/[...]/analog_mux_modified/veriloga/veriloga.va:50
     1 contribution MUX:/[...]/analog_mux_modified/veriloga/veriloga.va:60
[...]

Jorge,

My mistake. I made a typo in my modified netlist and actually the output of the mux was open circuit, not connected through the resistor-capacitor in series. I see the same messages you do.

I think in this case the discontinuity won't cause such a big problem because of the filtering, but if you want to avoid discontinuities in general (which is usually a good idea), there are some strategies covered in the Behavioral Modeling with Verilog-AMS course. This is available for free as an online course on Cadence Online Support - go to Learning->Online Courses and search for that course title and you'll find it free online. I suggest picking the latest version v20.09. Whilst it's for Verilog-AMS it has sections on smoothing analog discontinuities which are equally applicable to Verilog-A.

Andrew 

You might also want to take a look at https://web.archive.org/web/20180727105415/https://m.eet.com/media/1171788/ms-part4.pdf (from a chapter by Ron Vogelsong in the Mixed-Signal Methodology Guide).

Thank you Andrew and Frank for the pointers to those resources; I'll check them and give it another try!
Cheers, Jorge.