Signal doesn't reach full swing (0 -> VDD) in post-layout spectre tran-simulation

Dear Iqbal,

I can provide my initial thoughts as I have experienced the "symptoms" you are observing on a few occasions. However, without intimate knowledge about your layout, layout practices, power/ground routing methodologies, and schematic/symbol I can't really be certain any of these possible issues exist!

1. You noted you have not experienced this phenomena "... in other (smaller) designs." This suggests a couple of possibilities immediately to me.

a. If your subcircuit has dedicated power and ground pins, are you sure the layout has sufficient contacts connected to those pins? I have four, as have others, that often a layout designer may only connect the power pin or ground pin to one of what could be a "sea" of vias. As such, ALL the supply and ground current to the subcircuit is forced to flow through a single via. This may cause a very significant IR drop and result in some or all of your internal CMOS based circuits to have logic low and high values that are too high relative to ground or too low relative to the positive supply. The layout designer can easily address this by connecting sufficient layout pins to the symbol defined power and ground pins. The fact that you have not observed this phenomena with smaller circuits (whose currents to the supply and ground may be much less) is also consistent with this hypothesis.

b. Most layouts make use of a power and ground grid consisting of one or more upper layers of metal. As such, the layout for a subcircuit usually does not include the layers of the power and ground grid as it cannot use these layers for its routing. Hence, when an extracted view of the subcircuit is created for simulation, it does NOT include the low impedance planes the circuit will have in a higher level of the layout hierarchy where the power and ground planes are included. Hence, often it is necessary to ask your layout designer to make sure to include a "pseudo grid" in the subcircuit that approximates the power and ground grid within the subcircuit. This 'pseudo grid" is not retained in the layout when the subcircuit's layout is added to the next level of layout hierarchy.

2. Secondly, and perhaps it is too obvious to all, but study the power and ground routing strategy of your layout to make sure the IR drops to devices are within your required tolerances. The sheet resistance of lower metal layer metals in today's technologies are relatively large and it is often necessary to double and triple up on traces or lower metal layers to meet IR drop requirements.

Without more data, I tend to think your observed behavior is not a result of a simulator issue, but related to one of the aforementioned layout issues.

Just a few thoughts to (hopefully!) provide some food for thought for you Iqbal.

Shawn

Dear Shawn, thanks a lot for your help!

I excluded the IR-drop scenario before I posted my question here, because I expected the signals in that case to be a scald down version of the pre-layout signals, i.e. from VSS+ground_bounce to VDD-IR. But as the screenshot shows, the form of the signals is weird. That's why I focused  on spectre convergence issues. But you are right.

I ran the simulation with DC stimulus to see if exclude dynamic IR drop first. The form was slightly better. So I added decap cells to the design and re-ran the simulation and observed another improvement.

I tried all your suggestions one by one and with each step improving the form of the signals. 

The full-custom (cells as well as  P&R) design has  VDD and VSS rails on M1. The minimal sizes don't allow more the one source-contact. I originally connected all the rails to tackle some LVS issues.  So the power rails had this typical interleaved 'E' form:

-----------+

.......... |

: ---------+

.......... |

: ---------+

1.a: I removed  the 'E' wires and copied the VDD and VSS pins/labels to all the power rails. This improved the form. I suppose having pins only on the first

two wires and the 'E' thing caused the calibre xACT to connect the power rails in series(?).

1.b: I added a "pseudo grid" on M5 (Width  = 2 x W_min ) and connected it all the way down to the M1 power rails. This added to the improvement and solved the IR-drop problem. There is still some ground bounce (~ 25mv, @ 800mV VDD). Btw, I'm the layout designer... one-man-army on this project :)

2. I'm planning, in contrary to synthesis tools to add the power grid after all the sub-macros are placed and routed. So I try to leave space for the vias, etc. to connect M1 up to the M5-grid.

once again, thanks a lot and kind regards

Iqbal

Dear Shawn, thanks a lot for your help!

I excluded the IR-drop scenario before I posted my question here, because I expected the signals in that case to be a scald down version of the pre-layout signals, i.e. from VSS+ground_bounce to VDD-IR. But as the screenshot shows, the form of the signals is weird. That's why I focused  on spectre convergence issues. But you are right.

I ran the simulation with DC stimulus to see if exclude dynamic IR drop first. The form was slightly better. So I added decap cells to the design and re-ran the simulation and observed another improvement.

I tried all your suggestions one by one and with each step improving the form of the signals. 

The full-custom (cells as well as  P&R) design has  VDD and VSS rails on M1. The minimal sizes don't allow more the one source-contact. I originally connected all the rails to tackle some LVS issues.  So the power rails had this typical interleaved 'E' form:

-----------+

.......... |

: ---------+

.......... |

: ---------+

1.a: I removed  the 'E' wires and copied the VDD and VSS pins/labels to all the power rails. This improved the form. I suppose having pins only on the first

two wires and the 'E' thing caused the calibre xACT to connect the power rails in series(?).

1.b: I added a "pseudo grid" on M5 (Width  = 2 x W_min ) and connected it all the way down to the M1 power rails. This added to the improvement and solved the IR-drop problem. There is still some ground bounce (~ 25mv, @ 800mV VDD). Btw, I'm the layout designer... one-man-army on this project :)

2. I'm planning, in contrary to synthesis tools to add the power grid after all the sub-macros are placed and routed. So I try to leave space for the vias, etc. to connect M1 up to the M5-grid.

once again, thanks a lot and kind regards

Iqbal