Signal doesn't reach full swing (0 -> VDD) in post-layout spectre tran-simulation

Dear Iqbal,

I can provide my initial thoughts as I have experienced the "symptoms" you are observing on a few occasions. However, without intimate knowledge about your layout, layout practices, power/ground routing methodologies, and schematic/symbol I can't really be certain any of these possible issues exist!

1. You noted you have not experienced this phenomena "... in other (smaller) designs." This suggests a couple of possibilities immediately to me.

a. If your subcircuit has dedicated power and ground pins, are you sure the layout has sufficient contacts connected to those pins? I have four, as have others, that often a layout designer may only connect the power pin or ground pin to one of what could be a "sea" of vias. As such, ALL the supply and ground current to the subcircuit is forced to flow through a single via. This may cause a very significant IR drop and result in some or all of your internal CMOS based circuits to have logic low and high values that are too high relative to ground or too low relative to the positive supply. The layout designer can easily address this by connecting sufficient layout pins to the symbol defined power and ground pins. The fact that you have not observed this phenomena with smaller circuits (whose currents to the supply and ground may be much less) is also consistent with this hypothesis.

b. Most layouts make use of a power and ground grid consisting of one or more upper layers of metal. As such, the layout for a subcircuit usually does not include the layers of the power and ground grid as it cannot use these layers for its routing. Hence, when an extracted view of the subcircuit is created for simulation, it does NOT include the low impedance planes the circuit will have in a higher level of the layout hierarchy where the power and ground planes are included. Hence, often it is necessary to ask your layout designer to make sure to include a "pseudo grid" in the subcircuit that approximates the power and ground grid within the subcircuit. This 'pseudo grid" is not retained in the layout when the subcircuit's layout is added to the next level of layout hierarchy.

2. Secondly, and perhaps it is too obvious to all, but study the power and ground routing strategy of your layout to make sure the IR drops to devices are within your required tolerances. The sheet resistance of lower metal layer metals in today's technologies are relatively large and it is often necessary to double and triple up on traces or lower metal layers to meet IR drop requirements.

Without more data, I tend to think your observed behavior is not a result of a simulator issue, but related to one of the aforementioned layout issues.

Just a few thoughts to (hopefully!) provide some food for thought for you Iqbal.

Shawn

Dear Shawn, your answer is looking interesting for me, 

I have faced a similar problem and I have solved it by using pin layer that cover the entire power lines for the VDD and GND. 

However, since there is no physical meaning and there is no special fab process for pins, I would like to ask you if this only like a trick to pass the Cadence simulation?

because on the other side if I cover the entire rails with the pin layer, it will make the IR drop perfectly removed, which is not the practical thing

Thank you  

Dear Shawn, your answer is looking interesting for me, 

I have faced a similar problem and I have solved it by using pin layer that cover the entire power lines for the VDD and GND. 

However, since there is no physical meaning and there is no special fab process for pins, I would like to ask you if this only like a trick to pass the Cadence simulation?

because on the other side if I cover the entire rails with the pin layer, it will make the IR drop perfectly removed, which is not the practical thing

Thank you  

Of course, when simulating the effects of IR drop, you really have to think about how the supply will be connected into the block The tools cannot magically know what is going on outside of the block you're analysing. If you pretend that both ends are perfectly connected, and that makes a significant difference, you will need to be confident that the supply is very well connected across the supply net - otherwise you're just fooling yourself.

It's not a trick - it's just a good way of potentially getting the wrong answer. It's nothing to do with pins not having a special fab process - do you really think that fabs could convert a pin into a perfect conductor?

Andrew

Hi Senan,

in my case, the way I placed the pins only on the top two rails and the way I connected them ('E' thing) suggested to calibre to connect the rails as a "one long line" or a even a tree which increased the resistance on the line the thus the IR-drop. Placing pins on each rail (in this submacro 7x VDD and 6x VSS) and adding the (for now pseudo) grid reduced the resistance between the mosfet source contacts and the power rail. I hope some one would correct this assumption, if I'm wrong.

Kind regards,

Iqbal

Dear Iqbal,

Thank you, very much, for filling us in on your experiments and findings! I am very happy to read that your experiments did indeed provide some insight into your observations!

Thank you, also, Andrew for your comments. As you indicate, avoiding significant voltage drops due to this issue in layout and its impact on a simulation using an extracted view from the layout, is dependent on the power and ground strategy for the subcircuit of interest. 

It is acknowledged that adding in a "pseudo" power/ground layer (or the pins connecting to it) is not entirely equivalent to how the currents will flow in the top level layout hierarchy. As a result, our verification process includes simulating a subcircuit using its extracted view with some type of model for its power/ground included in the layout [1] and then verifying the cell's performance using the extracted view of the top level of layout hierarchy. The latter provides verification that the "estimated" layout model for the power/ground connections in subcircuit simulations is a reasonable model for the actual power/ground distribution network.

I hope my comments make some sense...and thank you, again, Igbal and Andrew (and your added comment/question too Senan)!

Shawn

[1] Note: the model for its power/ground is removed from the subcircuit layout before the cell layout is included in the next level of layout hierarchy.

Shawn,

In case of any confusion (I don't think you are, but just in case) I should have pointed out that my reply was to Senan, not the original poster or your suggestions... (I'd not noticed that Senan was not the original poster).

Andrew

Thank you Andrew very much for your response to my comment

Your explanation is quite clear and I believe in it, but I don't know why the PDK IP comes with pins covering the complete rails, that is what indeed made me misunderstanding this concept,

I agree with you that covering the rail with the pin is nothing but tricking or fooling myself, which means I have to put the pins only where I expect to have the connection to the supply ring after constructing the PAD frame,

let me ask you here please, if i have an op-amp cell and I have layout fllor plan that allow me to have the VDD&GND connection from the right and the left side only, it means for accurate modelling of the IR drop I should emulate this condition by making two pins of VDD and two pins of GND and i put them one to the right and one to the left, is this possible to have copy of the same pine at different places?

Thank you once again

Regards

Thank you iq79 for your reaction to my comment

Thank you Shawn for your nice and helpful explanation

Dear Senan,

Of course! To be honest, I am just happy to read it made sense to someone!! Thank you for letting me known and good luck!

Shawn