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Layour Passing LVS but failing passing PEX extracting calibre. Anyone know why?

FlyingAlbatross

Hello. I'm finding trouble when doing with extracting calibre from my layout. I post screenshots of my situation. I was doing an OR gate circuit layout. It successfully passed nmLVS. But when I was extracting calibre info by PEX, it reports 364 errors.

Above is the PEX error screenshot. PEX reports that a lot of nets are shorted with each other but I haven't made those mistakes during my connecting nets in layout. Otherwise, the layout couldn't pass LVS. The following screenshot was taken when I was opening the calibre view of the OR gate circuit. They look chaotic and seem to be wrong, but I don't know where the problems lie in. I'm confused and really need a hand. Sorry to ask such a basic question here but I'm a true green hand in cadence. Thank you to everyone clicking on this thread. Any kind of hints in how to deal with it would be very helpful for me and save me from anxiety. Thank you!!

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  • Andrew Beckett

    This question is all about Calibre LVS and PEX, which are not Cadence tools. Yes, you're running them from Virtuoso, and generating a calibre extracted view for use in Virtuoso, but all the tools you're using to do that are from Siemens EDA and so you would be better off asking this question in a Siemens EDA forum or via their customer support.

    I also moved this from Custom IC SKILL to Custom IC Design as it had absolutely nothing to do with SKILL.

    Regards,

    Andrew

Reply
  • Andrew Beckett

    This question is all about Calibre LVS and PEX, which are not Cadence tools. Yes, you're running them from Virtuoso, and generating a calibre extracted view for use in Virtuoso, but all the tools you're using to do that are from Siemens EDA and so you would be better off asking this question in a Siemens EDA forum or via their customer support.

    I also moved this from Custom IC SKILL to Custom IC Design as it had absolutely nothing to do with SKILL.

    Regards,

    Andrew

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