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adding delay element to circuit

Soly

I want to delay my signal by 1.5 ~ 2 nano second i tried to use two inverters but its doesn't give me large delay as i want.

The reason why i want to add delay

Im building receiver system and extracting clock using CDR to use it in the ADC

My eye diagram is wide open around 5 nano second but the rising edge of the extracted clock is at multiples of 3 nano seconds.

so i want delay the extracted clock by 1.5 ~ 2 nano seconds without affecting my clock

Eye diagram

extracted clock 

  • ShawnLogan

    Dear Soly,

    Soly said:

    so i want delay the extracted clock by 1.5 ~ 2 nano seconds without affecting my clock

    Did you examine the properties of the analogLib component vcvs I described yesterday? As shown in its properties in Figure 1, I have circled its programmable delay property. You may include a value in the circled property and it will delay the input signal. The delay parameter must be equal or greater than 0. As an example, I varied the delay of the element from 0 to 5 ns in 1 ns increments and plot the input and output signals in Figure 2.

    However, the use of the vcvs will eliminate any properties of the clock driving source (i.e., its output impedance any loading your ADC will present - which may mean this component may not meet your needs.

    I hope this helps Soly!

    Shawn

    Figure 1

    Figure 2

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