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Generate layout from symbols with design variables

James Yam

I created some schematic symbols which have some design variables (channel length pPar("L"), channel width pPar("W") ) of the MOSFETs being used inside the symbol). But when I generated a layout from this symbol (at a higher level schematic) through the "connectivity" in Virtuoso XL. The pcells could not shown correctly message ("Pcell Eval failed"). I have already set the parameter values of the symbols in the higher level scheamtic. But it seems that the parameter values could not be passed to the MOSFET devices inside the symbol during the layout generation.

What should I do?

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  • James Yam

    Thanks Andrew, my problem was solved. I found the following request's solution which worked for me. For sharing.

    https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000002JngkEAC&pageName=ArticleContent&caseSessionKey=0053w000008kZa9AAE__20220525163022917

    In summary, in the .cdsinit and .cdsenv, adding the following statements:

    In .cdsenv, the syntax is: layoutXL lxEvalCDFCallbacks 'boolean t

    In .cdsinit or CIW, the syntax is: envSetVal("layoutXL" "lxEvalCDFCallbacks" 'boolean t )

Reply
  • James Yam

    Thanks Andrew, my problem was solved. I found the following request's solution which worked for me. For sharing.

    https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000002JngkEAC&pageName=ArticleContent&caseSessionKey=0053w000008kZa9AAE__20220525163022917

    In summary, in the .cdsinit and .cdsenv, adding the following statements:

    In .cdsenv, the syntax is: layoutXL lxEvalCDFCallbacks 'boolean t

    In .cdsinit or CIW, the syntax is: envSetVal("layoutXL" "lxEvalCDFCallbacks" 'boolean t )

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