Top-Level RC Extraction with black box option

Hello

I have read the document Circuit Physical Verification and Parasitic Extraction, Rapid Adoption Kit (RAK), Product Version: PVS19.12, Quantus20.10 June 2020

In particular, I am interested in running the LVS for the top hierarchal level which includes already verified layout blocks. Hence the top abstract contains those cells plus the interconnection between them and to the pads.

According to this manual, it is recommended to run LVS by treating the lower layout cells as a back box. 

I couldn't understand from the manual the idea of black box because from what I read it looks to me that the tool treat those boxes as a box with the extended pins for next verification of LVS, and then the QRC extractor will  only exctract the parasatic of the top level connections.

Ofcourse I am not sure about my conclusion, but if my understanding is right it means the post-layout simulation will only reflect the fact due to the top-level parasitic.

It would be helpful if you explain me the advantage of black box and the difference in case if I used the regular LVS without black box.

Thank you in advance

Best Regards