Pnoise analysis of a clock divider with uneven even/odd output cycles

Dear csn165309964,

csn165309964 said:

I'm considering setting the pss period to twice the output period and the pnoise sample ratio to 2.

First, you need to set up your pss analysis correctly. If I understand your circuit, you are interested in simulating edge phase noise of a divider whose output transitions (rising or falling) are generated by alternating transition types of the input clock. In other words, the input and output transitions for a divider ratio of K might be as shown in Table 1. Am I correct in my understanding?

                     Table 1

Input  Clock              Output Clock (Divider = K)

Transition (x = 1,2,3)  Transition (N = 1,2,3...)

Number   Type        Number        Type

     Kx         Falling           2N-1     Falling or rising

     Kx+1     Rising           2N         Rising or falling

If so, since you are interested in simulating its edge phase noise, you must initially set up a PSS analysis for a driven divide-by-K circuit. If you have not read it yet, there are two Troubleshooting Articles that directly address setting up a PSS analysis and running a phase noise (pnoise) analysis for a divider driven by an input clock. The two are at URL:

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nTynEAE&pageName=ArticleContent

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009xzDeEAI&pageName=ArticleContent

The second article, I think, directly addresses your initial question about setting up the pss and pnoise output period and sample ratio. You mentioned using a sample ratio of 2 - but that does not sound right unless your divider ratio K is 2.

With regard to your question:

csn165309964 said:

ould the sample jitter analysis sample uniformly picking wrong crossing for the second edge, or sample the two actual crossings? In case it samples the two actual crossings, would the Edge Phase Noise calculation correctly consider the slightly different slopes of the two edges in converting the sampled noise into jitter?

As detailed in the second article, you will need to include measurements for the rising and falling edges of the output clock. Both analyses can be done with a single pss/pnoise set of simulations.

I hope this helps a little csn165309964...

Shawn

Hi Shawn,

Thanks for the reply. I read the two articles and found them helpful. I realized my question was misleading so updated my initial post with an illustration. I’m sorry for my unclear question and I hope my question is more clear this time.

Thanks,

Hi Shawn,

Thanks for the reply. I read the two articles and found them helpful. I realized my question was misleading so updated my initial post with an illustration. I’m sorry for my unclear question and I hope my question is more clear this time.

Thanks,

Dear csn165309964,

Thank you for providing the added information! I only wish I was smart enough to now understand - my apologies! 

What confuses me is what waveform you are showing - I thought you were going to show your divider's output waveform that from your description divides the input clock to the divider by 2. However, in 1 pss period, you are showing two input clock cycles.

csn165309964 said:

The output of the divider has uneven even/odd cycles as illustrated below.

You illustrate the "PSS period" as what looks like 2 clock cycles, but then noted in the following sentence:

csn165309964 said:

I'm considering setting the pss period to twice the output period as below and the pnoise sample ratio to 2.

The sample ratio is the the number of cycles of the output divider signal that is required for it to be truly periodic. I've annotated your diagram and hopefully that will convey myself lack of understanding given your statements.

Dear Shawn,

”… I thought you were going to show your divider’s output waveform …”

—> Yes, my illustration was the output waveform.

”… the PSS period … contains an alternating frequency of 1/AB followed by 1/AC …”

—> The PSS period in my illustration contains an alternating frequency of 1/AC followed by 1/(PSS_period-AC).

I added another illustration below to show both the input and the output and the PSS period.

Thanks,

Dear csn165309964,

Thank you again! I think I have it now. I assembled an annotated version of your latest Forum post timing diagram and wrote a few equations to describe the periodicity to use in a pss simulation, the relationship between the instantaneous frequencies of the two divider clocks comprising the pss period and the input clock duty cycle error as well as the duty cycle errors of the two clocks. The note is attached in Adobe Portable Document Format. Hopefully you agree - and please accept my sincerest apology if I still have not fully understood or made an error in my equations!

if you are not interested in the random noise, since the noise you are adding is deterministic(i.e., the resulting jitter will be of a deterministic nature and may dominate the random component), you might find it more efficient to perform a series of conventional transient analyses in lieu of pss/pnoise analyses.

Since the duty cycle error may show its greatest variation with process and environment, considering the impact of random noise might be worth examining under a "worse case environment", but perhaps not for every process and environment corner -just a thought.

And, yes, if you do follow through with an edge jitter pss/pnoise simulation set, the edge jitter of the output will show the effect of different transition times of the input clock as the noise will be modulated in relation to the steady-state transition times of the output. Each transition time of the output clock is a direct function of the slope of the input clock that produces it.

I hope this helps - and my apologies for not fully understanding your initial Forum post!

Shawn

divider_question_053122v1p0.pdf