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[SOLVED] [Verilog-A/AMS] Instantiating verilog-ams with analog input and digital output

delgsy

EDIT: solution: Change reg OUT; into wire OUT;


I instantiated verAMS_delay into verAMS_array_delay_v2.
both modules pass extraction.
Hierarchical editor recognizes the instantiated module but it shown in red like in the picture below.
When I tried to simulate it, it has the error below.
Could someone point me where I made mistake?



  • You need to specify the library name in the Library List. Verilog and Verilog-AMS instantiations do not bind the library (because there's no reference to the library name in the instantiation), so the hierarchy editor needs to be told the order of the list of libraries to search for modules (cells) to resolve such instantiations.

    Andrew

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