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Segmentation fault upon VerilogA compilation with an if condition

AAbdelRahman

Hi,

I am currently using ICADVM20.1-64b.500.24 and SPECTRE21.1.0.334.isr6 64bit. I already passed checksysconf for those and other cadence tools I currently have. My OS is CentOS 7. The server has 1TB of RAM, 64 cores (128 threads), and plenty of storage space. I am already using "unlimit stacksize"

When I compile the simple attached verilogA file, it gives away a segmentation fault. This is during compilation and not even simulations.

Fullscreen new_res_estim.txt Download 
// VerilogA for behavioral_blocks, new_res_estim, veriloga

`include "constants.vams"
`include "disciplines.vams"

module new_res_estim(in, sk, out);

input in, sk;
output out;

electrical in, sk, out;

parameter integer freeze = 0 from [0:1];

if (freeze == 0)
analog @(initial_step) $display("hello_world");

endmodule

When I change the condition to "freeze ==1" which is the opposite of what I want, it compiles successfully. When I change it "freeze!=1" it fails again.

Going back to an older version seems to fix the problem. For example, using ICADVM20.1 ISR21 and SPECTRE21.1 ISR1 compilation is successful.

I have been facing other "random segment faults" during simulations and I don't know if those things are somehow related.

Best regards.

Ahmed

  • Andrew Beckett

    Ahmed,

    I don't see this problem - it compiles successfully with me. I suggest you contact customer support.

    Andrew

  • delgsy

    curious with hello_world in verilogA so I tried to compile it.
    well, just want to say, It compiles ok on my pc.

  • AAbdelRahman
    in reply to Andrew Beckett

    Hi Andrew,

    Thanks for your reply.

    I will do that.

    Best regards,

    Ahmed

  • AAbdelRahman
    in reply to delgsy

    Hi Delgsy,

    Thanks for letting me know.

    Best regards,

    Ahmed

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