Stats

  • Locked Locked
  • Replies 2
  • Subscribers 125
  • Views 9364
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Pegasus LVS: how to enforce agreement of fins-per-finger parameter?

dontpanic

Hi! How can I make Pegasus to enforce checking the same number of fins per finger in both schematic and layout devices?

Currently, this is being ignored in my setup. For example: a schematic device made of 6 fingers and 8 fins per finger passes LVS against a layout device of 8 fingers and 6 fins per finger.

In both cases the total number of fins is 48, but there are 2nd-order effects that make it really important to have exact agreement between the number of fins per finger in schematic and layout.

I tried looking in the documentation (e.g. "Cadence Pegasus Developers Guide 21.31"), but got really lost in the sea of options and parameters.

Thanks in advance for any help!

Jorge.

P.S. In attachment an excerpt of the LVS options I'm using, as reported in the .rep.cls file from Pegasus.

  • dontpanic

    ##############################################################################################################
    #
    #                                                  LVS RULES                                                  
    #
    ##############################################################################################################

    LVS Rules Given in the Rules File
    ---------------------------------

        lvs_abort                               -softchk                               no  
        lvs_abort                               -supply_error                          no  
        layout_case_sensitive                   yes
        layout_format                           gdsii
        layout_format                           GDSII
        layout_primary                          lvs_top
        schematic_case_sensitive                yes
        schematic_format                        cdl
        schematic_primary                       lvs_top
        lvs_push_devices_properties             yes
        lvs_spice                               yes -prefer_pins
        lvs_spice                               yes -replicate_devices
                                                 
        lvs_compare_case                        NAMES TYPES SUBTYPES VALUES
        lvs_power_name                          vdd
        lvs_power_name                          AHVDD AHVDDB AHVDDG AHVDDR AHVDDWELL AVDD AVDDB AVDDBG AVDDG AVDDR
                                                AVDWELL DHVDD DVDD HVDDWELL TACVDD TAVD33 TAVD33PST TAVDD TAVDDPST
                                                TVDD VD33 VDD VDD5V VDDESD VDDG VDDM VDDPST VDDSA VDWELL  
        lvs_ground_name                         vss
        lvs_ground_name                         AGND AHVSS AHVSSB AHVSSG AHVSSR AHVSSUB AVSS AVSSB AVSSBG AVSSG
                                                AVSSR AVSSUB DHVSS DVSS GND HVSSUB TACVSS TAVSS TAVSSPST TVSS VS33
                                                VSS VSSESD VSSG VSSM VSSPST VSSUB  
                                                 
        lvs_all_cap_pins_swappable              yes
        lvs_ignore_ports                        no  
        lvs_compare_port_names                  yes
        lvs_find_shorts                         no  
        lvs_break_ambig_max                     1000
                                                 
        lvs_filter_option                       AG RC RE RG -source_layout
                                                 
        lvs_reduce_split_gates                  yes ...
        lvs_recognize_gates                     -NONE
        lvs_reduce                              no  -parallel_bipolar
        lvs_reduce                              no  -parallel_mos
        lvs_reduce                              no  -parallel_diodes
        lvs_reduce                              no  -parallel_caps
        lvs_reduce                              no  -parallel_resistors
        lvs_reduce                              no  -series_resistors
        lvs_reduce                              no  -series_caps

                                                 
        lvs_expand_cell_on_error                yes
                                                 

        lvs_report_max                          50 -mismatched_net_limit 100
        unit                                    -length u
        input_scale                             10000
        virtual_connect                         yes -colon
        virtual_connect                         no  -semicolon_as_colon
        virtual_connect                         no  -report
        virtual_connect                         -depth primary
        text_depth                              -primary
        text_depth                              -PRIMARY
        port                                    -depth -PRIMARY
                                                 

    Default LVS Rule Values
    -----------------------

        lvs_abort                               -check_device_for_property_rule no
        lvs_abort                               -missing_hcell no
        lvs_abort                               -erc_error yes
        // layout_cpf_file                       
        // schematic_cpf_file                    
        // hcell_file                            
        // hcell                                 
        // lvs_exclude_hcell                     
        // lvs_delete_cell                       
        lvs_push_devices                        yes
        lvs_netlist                             yes -substrate_comment
        lvs_netlist                             yes -box_contents
        lvs_netlist                             yes -unnamed_box_pins
        lvs_netlist                             no -allow_inconsistent_model
        lvs_netlist                             yes -properties_comment
        // lvs_write_netlist                     
        // lvs_write_netlist_reduced             
        // lvs_delete_cell_pin                   
        // lvs_black_box                         
        // lvs_interposer                        
        lvs_spice                               yes -allow_floating_pins
        lvs_spice                               yes -allow_duplicate_subcircuit_names
        lvs_spice                               no  -conditional_ldd
        lvs_spice                               no  -override_globals
        lvs_spice                               no  -redefine_param
        lvs_spice                               no  -replicate_devices_enhanced
        lvs_spice                               yes -slash_is_space
        lvs_spice                               yes -keep_back_slash
        lvs_spice                               no  -allow_unquoted_strings
        lvs_spice                               no  -allow_inline_parameters
        lvs_spice                               no  -calculate_mos_area
        lvs_spice                               no  -strict_wl
        lvs_spice                               no  -cull_primitive_subcircuits
        lvs_spice                               no  -ignore_option_scale
        lvs_spice                               no  -show_neg_param_warning
        lvs_spice                               no  -scale_x_parameters
        lvs_spice                               yes -strict_subckts_order
        // lvs_spice_option                      
        lvs_reverse_wl                          no
        // lvs_spice_multiplier_name             
                                                 
        lvs_cname                               yes -pin
        lvs_cname                               yes -net
        lvs_cname                               no  -instance
        lvs_non_user_name                       -port "^[0-9]+$"
        lvs_non_user_name                       -net  "^[0-9]+$"
        // lvs_non_user_name                    -instance
        lvs_out_of_range_exclude_zero           no
        // lvs_group_models                      
        lvs_strict_subtypes                     no
        lvs_exact_subtypes                      no
        lvs_preserve_box_ports                  no
        // lvs_cpoint                            
        // lvs_cell_list                         
                                                 
        lvs_auto_pin_swap                       yes -swap_threshold 4000000
        lvs_swap_non_cpoint_pins                yes
        // lvs_swap_pins                         
        lvs_builtin_device_pin_swap             yes
        // lvs_join_nets                         
        lvs_global_sigs_are_ports               yes
        lvs_discard_pins                        no
                                                 
        lvs_filter                              no  -bipolar
        lvs_filter                              no  -capacitors
        lvs_filter                              no  -diodes
        lvs_filter                              no  -mos
        lvs_filter                              no  -resistors
                                                 
        lvs_reduction_priority                  -parallel
        lvs_derive_logic                        yes -sram
        lvs_derive_logic                        no  -dram
        lvs_derive_logic                        no  -rom
        // lvs_recognize_gates_tolerance         
        lvs_reduce                              no  -series_diodes
        lvs_reduce                              no  -series_mos
        // lvs_reduce_do_not_merge               
                                                 
        lvs_expand_on_device_climbing           no
        lvs_expand_unbalanced_cells             yes
                                                 
        // lvs_check_all_properties_by_name      
        // lvs_property_map                      
        // lvs_transfer_property                 
        lvs_warn_max                            50
        // lvs_report_opt                        
        lvs_report_units                        yes
        lvs_keep_data                           no
        lvs_keep_source_cells                   no
        lvs_create_match_db                     no
        // lvs_map_device                        
        unit                                    -resistance ohm
        unit                                    -capacitance pf
        lvs_verilog_bus_map_by_position         no
        lvs_verilog_keep_backslash              no
        lvs_verilog_detect_buses                no
        lvs_do_not_normalize                    no
        // lvs_generic_device                    
        virtual_connect                         no  -colon
        virtual_connect                         yes -semicolon_as_colon
        // virtual_connect                      -name
        virtual_connect                         no -report
        virtual_connect                         no -incremental
        lvs_preserve_parameterized_cells        no
        lvs_check_color                         no
        // lvs_schematic_color_path              
        // lvs_assign_conflict_layer             
        // lvs_conflict_layer_check             
        lvs_check_color_label                   no
        // lvs_preserve_cells                    
                                                 

    Effective LVS Rule Values
    -------------------------

        lvs_swap_non_cpoint_pins                yes -unbound_pin_threshold 10000
        lvs_filter_option                       AG RC RE RG -source
        lvs_filter_option                       AG RC RE RG -layout
        lvs_derive_logic                        no   -sram
        lvs_reduce                              yes -parallel_mos
        virtual_connect                         yes -colon
        virtual_connect                         no  -semicolon_as_colon
        virtual_connect                         no  -report
        text_depth                              -primary

  • Andrew Beckett
    in reply to dontpanic

    Jorge,

    Probably best (if you've not found an answer so far) to contact customer support for this.

    Andrew

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.