Verilog netlist wont explicit bit connected to bus pin

Hi, 

Im using verilog netlister (lunch--> plugins-->simuilation--> systemVerilog) to netlist my schematic. 

Now I have an instance with 32 bit pin input (input rstb<31:0>). 

In the schematic I connected a net to between this pin to one pin output of other instance. 

Now the schematic (and any analog netlister ) is smart enough to understand that this 1 pin should drive the all 32 bit. 

But when creating verilog netlis it will connect only bit (something like  .rts_b(father_1_bit_net) ... ). 

  Actually I know this thing will depend on the various env variable and I do have .simrc file looks something like this: 

simVerilogNetlistExplicit = 't
hnlVerilogNetlistBehavioralExplicit = 't
hnlVerilogNetlistNonStopCellExplicit = 't
simVerilogTestFixtureFlag = 'nil
simVerilogTestFixtureTemplate = 'nil
vlogifInternalTestFixtureFlag = 'nil
hnlVerilogTermSyncUp = "mergeAll"
simVerilogDropPortRange = 't
 

Version: ICADVM20.1-64b.500.24