3-bit flash ADC design

Dear Lohithpras,

Lohithpras said:

i'm trying to simulate the 3-bit flash adc design but i keep getting" ERROR (USIMDB-11501): The UltraSim simulator encountered illegal voltage
source and inductor loop in the instance (element or node) '' in the
subcircuit ''. Check the instance before running the simulation again".

I will apologize in advance, but I don't think I have enough information to provide a more specific suggestion. It would be most useful if you provided your netlist with its comparator and multiplexer subcircuits. Andrew also suggests you always include the version of the tool you are using. The schematic is helpful, but its resolution does not allow me to see the instance numbers for all your "comp" and "mux" subcircuits - nor the models or circuit contents of either!

I believe the error is likely due to your model for "comp" as I suspect it may be a veriloga based subcircuit. Is this correct Lohithpras? It is quite common for subcircuits based on veriloga code of an ideal component to create a "loop of rigid branches". I suspect that your veriloga code for your "comp" instances may unintentionally create a short between two ideal voltage sources. You might take a look at this Forum post from about a year ago whose poster experienced a similar issue:

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/48157/fatal-the-following-branches-form-a-loop-of-rigid-branches-shorts-when-added-to-the-circuit

Once again, I apologize for not being able to provide a more specific suggestion, but I simply do not have sufficient information about your circuit and its components!

Shawn

Dear Lohithpras,

Lohithpras said:

i'm trying to simulate the 3-bit flash adc design but i keep getting" ERROR (USIMDB-11501): The UltraSim simulator encountered illegal voltage
source and inductor loop in the instance (element or node) '' in the
subcircuit ''. Check the instance before running the simulation again".

I will apologize in advance, but I don't think I have enough information to provide a more specific suggestion. It would be most useful if you provided your netlist with its comparator and multiplexer subcircuits. Andrew also suggests you always include the version of the tool you are using. The schematic is helpful, but its resolution does not allow me to see the instance numbers for all your "comp" and "mux" subcircuits - nor the models or circuit contents of either!

I believe the error is likely due to your model for "comp" as I suspect it may be a veriloga based subcircuit. Is this correct Lohithpras? It is quite common for subcircuits based on veriloga code of an ideal component to create a "loop of rigid branches". I suspect that your veriloga code for your "comp" instances may unintentionally create a short between two ideal voltage sources. You might take a look at this Forum post from about a year ago whose poster experienced a similar issue:

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/48157/fatal-the-following-branches-form-a-loop-of-rigid-branches-shorts-when-added-to-the-circuit

Once again, I apologize for not being able to provide a more specific suggestion, but I simply do not have sufficient information about your circuit and its components!

Shawn

It looks to me (from the error message) that you have voltage sources inside the "comp" component (my guess called V2 and V4 connected to the clk and vin pins) and these have ended up being in parallel with the top-level voltage sources in the schematic you showed. That's not allowed (you're using Ultrasim here, but it's the same in Ultrasim and Spectre - two ideal voltage sources in parallel creates an unsolvable circuit, even if they are the same voltage because the simulator cannot calculate how much current would flow in each; if they are different voltages it can't resolve the voltage at the node connected to the source).

Andrew