Vco design virtuoso

Dear Psyliver,

Psyliver said:

I suppose that only the interconnects should count as parasitics and not the components themselves.

Please allow me to comment on your assumption in case you had not considered it. If it is obvious to you Psyliver, please excuse my response and comment!

Although this may seem to be a simple "yes" or "no" answer, one must consider the details of your comment. Specifically, the demarcation between a "component" and the "parasitics" as you describe them is not well defined. If you are simulating a netlist that uses a schematic model for a component, it may contain additional elements in addition to the core component to estimate the parasitic elements that will be included in an actual physical layout. These additional elements are estimates only since a physical layout of the component does not exist. The additional elements added are dependent on the specific PDK.

When the netlist contains a component based on a physical layout, the model for the component chosen may be NOT the same as that for the schematic view based netlist as the PDK will substitute a core device model without any added estimated parasitic elements since the actual parasitic elements will be included in the physical layout.

Why is this done in some PDK? The location of the pins for a component are not always well defined. For example, in your varactor case, where is the actual gate terminal? There will always be some metal to contact the physical gate which will decrease its Q. A similar situation exists for its source/drain contact. As a result, if the tsmc varactor model does not include some metal in the gate and source/drain, it is impossible for it to properly model any physical realization of the varactor. Clearly, the varactor "alone in a layout" with pins must contain some metal features to at least contact the various layers. 

I might suggest you examine the two models that are called in the schematic view based simulation and the model used in the extracted view based layout to compare what, if any, additional components are included in addition to the "code" varactor model. My guess is you will find the model used in your schematic view based simulation does not contain any additional elements in addition to the core varactor model (or does not estimate proper values). Hence, at a given frequency (28 GHz,  its simulated Q will be much greater than the Q when simulated in an actual physical layout of the component.

Is my explanation clear at all Psyliver? I hope so..

Shawn

Dear Psyliver,

Psyliver said:

I suppose that only the interconnects should count as parasitics and not the components themselves.

Please allow me to comment on your assumption in case you had not considered it. If it is obvious to you Psyliver, please excuse my response and comment!

Although this may seem to be a simple "yes" or "no" answer, one must consider the details of your comment. Specifically, the demarcation between a "component" and the "parasitics" as you describe them is not well defined. If you are simulating a netlist that uses a schematic model for a component, it may contain additional elements in addition to the core component to estimate the parasitic elements that will be included in an actual physical layout. These additional elements are estimates only since a physical layout of the component does not exist. The additional elements added are dependent on the specific PDK.

When the netlist contains a component based on a physical layout, the model for the component chosen may be NOT the same as that for the schematic view based netlist as the PDK will substitute a core device model without any added estimated parasitic elements since the actual parasitic elements will be included in the physical layout.

Why is this done in some PDK? The location of the pins for a component are not always well defined. For example, in your varactor case, where is the actual gate terminal? There will always be some metal to contact the physical gate which will decrease its Q. A similar situation exists for its source/drain contact. As a result, if the tsmc varactor model does not include some metal in the gate and source/drain, it is impossible for it to properly model any physical realization of the varactor. Clearly, the varactor "alone in a layout" with pins must contain some metal features to at least contact the various layers. 

I might suggest you examine the two models that are called in the schematic view based simulation and the model used in the extracted view based layout to compare what, if any, additional components are included in addition to the "code" varactor model. My guess is you will find the model used in your schematic view based simulation does not contain any additional elements in addition to the core varactor model (or does not estimate proper values). Hence, at a given frequency (28 GHz,  its simulated Q will be much greater than the Q when simulated in an actual physical layout of the component.

Is my explanation clear at all Psyliver? I hope so..

Shawn

Thank you for your answer. My question arises from the option Transistor level or gate level in calibre PEX for the paracitic extraction. I read that gate level calculates only the interconnects and treats everything else as black boxes where in Transistor level i see a larger number of paracitics. The tsmc varactor from the other side had a anode and a cathode,both in metal 2 and a body in metal 1. So i only placed pins in the same layers. Meaning i put a pin metal 2 in anode which is again metal 2. So no Extra resistance is added. What i want to cite here is that how it possible with no interconnects and with just the pin placement the Q is so bad?. And why in schematic simulation is so good